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PDF AD5379 Data sheet ( Hoja de datos )
| Número de pieza | AD5379 | |
| Descripción | Bipolar Voltage-Output DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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40-Channel, 14-Bit, Parallel and
Serial Input, Bipolar Voltage-Output DAC
AD5379
FEATURES
40-channel DAC in 13 mm × 13 mm 108-lead CSPBGA
Guaranteed monotonic to 14 bits
Buffered voltage outputs
Output voltage span of 3.5 V × VREF(+)
Maximum output voltage span of 17.5 V
System calibration function allowing user-programmable
offset and gain
Pseudo differential outputs relative to REFGND
Clear function to user-defined REFGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
DAC increment/decrement mode
Channel grouping and addressing features
Interface options:
Parallel interface
DSP/microcontroller-compatible, 3-wire serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
SDO daisy-chaining option
Power-on reset
Digital reset (RESET pin and soft reset function)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
RESET
FIFOEN
DCEN/WR
SYNC/CS
REG0
REG1
DB13
SCLK/DB12
DIN/DB11
DB0
A7
A0
SER/PAR
DIN
SCLK
SDO
REFGND B1
REFGND B2
REFGND C1
REFGND C2
REFGND D1
REFGND D2
FUNCTIONAL BLOCK DIAGRAM
VCC
VDD VSS AGND
DGND
LDAC
VBIAS VREF1(+) VREF1(–) REFGND A1
POWER-ON
RESET
AD5379
VBIAS
/ /14
INPUT
REG
14
0–1
m REG0–1
/14
c REG0–1
/ /14 INPUT 14
REG
2
m REG2
14/
/14
c REG2
/ /14
DAC
REG
14
DAC 0–1
0–1
/ /14
DAC 14
REG
DAC 2
2
/ /14
INPUT
REG
14
7
m REG7
/14 c REG7
/ /14
DAC
REG
14
DAC 7
7
BUSY
/ /14
INPUT
REG
14
8–9
m REG8–9
/14 c REG8–9
/ /14
DAC
REG
14
DAC 8–9
8–9
×4
Figure 1.
VREF2(+) VREF2(–) REFGND A2
CLR
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT39
AD5379—Protected by U.S. Patent No. 5,969,657.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2009 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
AD5379
SPECIFICATIONS
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = 5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND = 0 V;
VBIAS = 5 V; CL = 200 pF to GND; RL = 11 kΩ to 3 V; gain = 1; offset = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
VOUT Temperature Coefficient
DC Crosstalk2
REFERENCE INPUTS2
VREF(+) DC Input Impedance
VREF(−) DC Input Impedance
VREF(+) Input Current
VREF(+) Range
VREF(−) Range
REFGND INPUTS2
DC Input Impedance
Input Range
OUTPUT CHARACTERISTICS2
Output Voltage Range
Short-Circuit Current
Load Current
Capacitive Load
DC Output Impedance
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current (with pull-up/pull-down)
Input Current (no pull-up/pull-down)
Input Capacitance2
DIGITAL OUTPUTS (BUSY, SDO)
Output Low Voltage
Output High Voltage (SDO)
High Impedance Leakage Current
High Impedance Output Capacitance2
POWER REQUIREMENTS
VCC
VDD
VSS
A Version1
14
±3
±2.5
−1/+1.5
±12
±5
±12
±8
±8
±1/±5
5
0.5
1
8
±10
1.5/5
−3.5/0
80
±0.5
VSS + 2/VSS + 2.5
VDD − 2/VDD − 2.5
15
±1.5
2200
1
1.7
2.0
0.8
±8
±1
10
0.5
VCC − 0.5
−70
10
2.7/5.5
8.5/16.5
−3/−16.5
Unit Test Conditions/Comments2
Bits
LSB max
LSB max
LSB max
mV max
mV max
mV max
mV max
mV max
mV typ/max
ppm FSR/°C typ
mV max
−40°C to +85°C
0°C to 70°C
Guaranteed monotonic by design over temperature
−40°C to +85°C
0°C to 70°C
−40°C to +85°C
0°C to 70°C
−40°C to +85°C
0°C to 70°C
Includes linearity, offset, and gain drift (see Figure 11)
Typically 100 μV
MΩ min
kΩ min
μA max
V min/max
V min/max
Typically 100 MΩ
Typically 12 kΩ
Per input (typically ±30 nA)
±2% for specified operation
±2% for specified operation
kΩ min
V min/max
Typically 120 kΩ
V min
V max
mA max
mA max
pF max
Ω max
V min
V min
V max
μA max
μA max
pF max
ILOAD = ±0.5 mA/±1.5 mA
ILOAD = ±0.5 mA/±1.5 mA
JEDEC compliant
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
VCC = 2.7 V to 5.5 V
SER/PAR, FIFOEN, and RESET pins only
All other digital input pins
V max
V min
μA max
pF typ
V min/max
V min/max
V min/max
Sinking 200 μA
Sourcing 200 μA
SDO only
Rev. B | Page 4 of 28
Free
5 Page 
AD5379
REG0,
REG1,
A7–A02
CS
t4
WR
DB12–DB0
BUSY
LDAC1
VOUT
t0 t1
t5
t2
t3
t6
t7
t9
t8
t10
t13
t11
t14
LDAC2
VOUT
CLR
t20
VOUT
1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE AFTER BUSY
t22
RESET
t21
t16
t12
t19
t15
t17 t14
t18 t19
VOUT
BUSY
t21
t23
Figure 6. Parallel Interface Timing Diagram
Rev. B | Page 10 of 28
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD5379.PDF ] | |
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