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A3973 Schematic ( PDF Datasheet ) - Allegro MicroSystems

Teilenummer A3973
Beschreibung Dual DMOS Full-Bridge Microstepping PWM Motor Driver
Hersteller Allegro MicroSystems
Logo Allegro MicroSystems Logo 




Gesamt 11 Seiten
A3973 Datasheet, Funktion
A3973
Dual DMOS Full-Bridge Microstepping PWM Motor Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 1, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, refer to the A3992.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Free Datasheet http://www.datasheet4u.com/






A3973 Datasheet, Funktion
A3973
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 5.0 V, VS = 0.5 V,
fPWM < 50 kHz (unless otherwise noted).
Limits
Characteristics
Symbol Test Conditions
Min. Typ. Max.
Control Logic (continued)
Internal Oscillator
fOSC
DAC Accuracy (total error)
ET
OSC shorted to ground
ROSC = 51 k
Relative to DAC reference buffer
output, D0 = 0, D17 = 0
3.0 4.0 5.0
3.4 4.0 4.6
— ±1/2 —
Reference Input Voltage Range VREF(EXT)
Reference Buffer Offset
VOS
Reference Divider Ratio
VREF/VS
D0 = 0, D18 = 0
D0 = 0, D18 = 1
0.5 — 2.6
— ±10 —
— 8.0 —
— 4.0 —
Reference Input Current
IREF
VREF = 2.0 V
Internal Reference Voltage
VREF(INT)
Gain (Gm) Error (note 3)
EG D0 = 0, D17 = 0,
    D18 = 0, DAC = 63
    D18 = 0, DAC = 31
    D18 = 1, DAC = 63
— — ±0.5
1.94 2.0 2.06
— 0 ±6
— 0 ±9
— 0 ±6
    D18 = 1, DAC = 15
— 0 ±10
Comparator Input Offset Voltage
VIO
VREF = 0 V
Propagation Delay Times
tpd 50% to 90%:
    PWM change to source on
    PWM change to source off
    PWM change to sink on
— ±5.0 —
500 800 1200
50 150 350
500 800 1200
    PWM change to sink off
50 150 350
Crossover Dead Time
tdt
300
Thermal Shutdown Temperature
TJ
Thermal Shutdown Hysteresis
TJ
UVLO Enable Threshold
VUVLO
Increasing VDD
3.9
UVLO Hysteresis
VUVLO
0.05
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. EG = [(VREF/Range) – VS]/(VREF/Range).
700
165
15
4.2
0.10
900
4.45
Units
MHz
MHz
LSB
V
mV
µA
V
%
%
%
%
mV
ns
ns
ns
ns
ns
°C
°C
V
V
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Free Datasheet http://www.datasheet4u.com/

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