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PDF CAT1021 Data sheet ( Hoja de datos )
| Número de pieza | CAT1021 | |
| Descripción | (CAT1021 - CAT1023) Supervisory Circuits | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CAT1021 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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CAT1021, CAT1022, CAT1023
Supervisory Circuits with I2C Serial 2k-bit CMOS
EEPROM, Manual Reset and Watchdog Timer
FEATURES
Precision Power Supply Voltage Monitor
— 5 V, 3.3 V and 3 V systems
— Five threshold voltage options
Watchdog Timer
Active High or Low Reset
— Valid reset guaranteed at VCC = 1 V
400 kHz I2C Bus
2.7 V to 5.5 V Operation
Low power CMOS technology
16-Byte Page Write Buffer
Built-in inadvertent write protection
— WP pin (CAT1021)
1,000,000 Program/Erase cycles
Manual Reset Input
100 year data retention
Industrial and extended temperature ranges
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 3 mm foot-print) packages
— TDFN max height is 0.8 mm
For Ordering Information details, see page 19.
DESCRIPTION
The CAT1021, CAT1022 and CAT1023 are complete
memory and supervisory solutions for microcontroller-
based systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection are
integrated together in low power CMOS technology.
Memory interface is via a 400 kHz I2C bus.
The CAT1021 and CAT1023 provide a precision VCC
sense circuit and two open drain outputs: one (RESET)
drives high and the other (R¯¯E¯S¯E¯T¯) drives low whenever
VCC falls below the reset threshold voltage. The
CAT1022 has only a R¯¯E¯S¯E¯T¯ output and does not have
a Write Protect input. The CAT1021 also has a Write
Protect input (WP). Write operations are disabled if WP
is connected to a logic high.
All supervisors have a 1.6 second watchdog timer circuit
that resets a system to a known state if software or a
hardware glitch halts or “hangs” the system. For the
CAT1021 and CAT1022, the watchdog timer monitors
the SDA signal. The CAT1023 has a separate watchdog
timer interrupt input pin, WDI.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5 V, 3.3 V and 3 V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200 ms after the supply voltage
exceeds the reset threshold level. With both active high
and low reset signals, interface to microcontrollers and
other ICs is simple. In addition, the R¯¯E¯S¯E¯T¯ pin or a
separate input, ¯M¯R¯, can be used as an input for push-
button manual reset capability.
The on-chip, 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided
by a VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until VCC
reaches the reset threshold during power up.
Available packages include an 8-pin DIP and surface
mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin
MSOP packages. The TDFN package thickness is
0.8mm maximum. TDFN footprint options are 3 x 3mm.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-3009 Rev. P
Free Datasheet http://www.datasheet4u.com/
1 page  
CAPACITANCE
TA = 25ºC, f = 1.0 MHz, VCC = 5 V
Symbol
COUT (1)
CIN(1)
Test
Output Capacitance
Input Capacitance
CAT1021, CAT1022, CAT1023
Test Conditions
VOUT = 0 V
VIN = 0 V
Max
8
6
Units
pF
pF
AC CHARACTERISTICS
VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol Parameter
Min Max
fSCL Clock Frequency
tSP Input Filter Spike Suppression (SDA, SCL)
400
100
tLOW Clock Low Period
1.3
tHIGH
tR(1)
tF(1)
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
0.6
300
300
tHD; STA
tSU; STA
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
0.6
0.6
tHD; DAT
tSU; DAT
Data Input Hold Time
Data Input Setup Time
0
100
tSU; STO Stop Condition Setup Time
0.6
tAA SCL Low to Data Out Valid
900
tDH
tBUF(1)
tWC(3)
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
50
1.3
5
Units
kHz
ns
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
ns
µs
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-3009 Rev. P
Free Datasheet http://www.datasheet4u.com/
5 Page 
CAT1021, CAT1022, CAT1023
Page Write
The CAT1021/22/23 writes up to 16 bytes of data in
a single write cycle, using the Page Write operation.
The page write operation is initiated in the same
manner as the byte write operation, however instead
of terminating after the initial byte is transmitted, the
Master is allowed to send up to 15 additional bytes.
After each byte has been transmitted, the
CAT1021/22/23 will respond with an acknowledge
and internally increment the lower order address bits
by one. The high order bits remain unchanged.
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter
‘wraps around,’ and previously transmitted data will be
overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1021/22/23 in a single write cycle.
Figure 8. Byte Write Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
BYTE
ADDRESS
A
C
K
A
C
K
DATA
S
T
O
P
P
A
C
K
Figure 9: Page Write Timing
S
T
BUS ACTIVITY:
MASTER
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SDA LINE S
AA
CC
KK
DATA n
DATA n+1
AA
CC
KK
S
T
DATA n+15
O
P
P
A
C
K
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-3009 Rev. P
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CAT1021.PDF ] | |
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