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PE83336 Schematic ( PDF Datasheet ) - Peregrine Semiconductor

Teilenummer PE83336
Beschreibung 3.0 GHz Integer-N PLL
Hersteller Peregrine Semiconductor
Logo Peregrine Semiconductor Logo 




Gesamt 14 Seiten
PE83336 Datasheet, Funktion
Product Description
Peregrine’s PE83336 is a high performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
superior phase noise performance of the PE83336 makes
it ideal for rugged military environments including: radio
handsets, radar, avionics, missiles, etc.
The PE83336 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial
or parallel interface and can also be directly hard wired.
Fabricated in Peregrine’s patented UTSi® (Ultra Thin
Silicon) CMOS technology, the PE83336, while optimized
for stringent military environments, offers excellent RF
performance together with the economy and integration of
conventional CMOS.
PRODUCT SPECIFICATION
PE83336
Military Operating Temperature Range
3.0 GHz Integer-N PLL for Low
Phase Noise Applications
Features
3.0 GHz operation
÷10/11 dual modulus prescaler
Internal phase detector
Serial, parallel or hardwired
programmable
Ultra-low phase noise
Available in 44-lead CQFJ
Figure 1. Block Diagram
Fin Prescaler
Fin 10 / 11
D(7:0)
8
Sdata
Primary
20-bit
Latch 20
Pre_en
M(6:0)
A(3:0)
R(3:0)
fr
Secon-
dary
20-bit
Latch
20
20
20
16
Main
Counter
13
66
R Counter
fp
Phase
Detector
PD_U
PD_D
fc
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 14
Free Datasheet http://www.datasheet4u.com/






PE83336 Datasheet, Funktion
PE83336
Product Specification
Table 5. DC Characteristics
VDD = 3.0 V, -55° C TA 125° C, unless otherwise specified
Symbol
Parameter
IDD Operational supply current;
Prescaler disabled
Prescaler enabled
Digital Inputs: All except fr, R0, Fin, Fin
VIH High level input voltage
VIL Low level input voltage
IIH High level input current
IIL Low level input current
Reference Divider input: fr
IIHR High level input current
IILR Low level input current
R0 Input (Pull-up Resistor): R0
IIHRO High level input current
IILRO Low level input current
Counter and phase detector outputs: fc, fp, PD_D, PD_U
VOLD
Output voltage LOW
VOHD
Output voltage HIGH
Lock detect outputs: Cext, LD
VOLC
VOHC
VOLLD
Output voltage LOW, Cext
Output voltage HIGH, Cext
Output voltage LOW, LD
Conditions
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
Iout = 6mA
Iout = -3mA
Iout = 100uA
Iout = -100uA
Iout = 6mA
Min
0.7 x VDD
-1
-100
-5
VDD - 0.4
VDD - 0.4
Typ Max Units
10 mA
20 28 mA
0.3 x VDD
+70
V
V
µA
µA
+100
µA
µA
+70 µA
µA
0.4 V
V
0.4 V
V
0.4 V
Copyright Peregrine Semiconductor Corp. 2003
Page 6 of 14
File No. 70/0137~01A
|
UTSi CMOS RFIC SOLUTIONS
Free Datasheet http://www.datasheet4u.com/

6 Page









PE83336 pdf, datenblatt
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 10. Enhancement Register Bit Functionality
Bit Function
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Reserved**
Reserved**
Reserved**
Power down
Counter load
Bit 5
MSEL output
Bit 6 Prescaler output
Bit 7
fp, fc OE
** Program to 0
Description
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and
Smode inputs.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the raw internal prescaler output onto the Dout output.
fp, fc outputs disabled.
PE83336
Product Specification
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D. If
the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses “low”.
If the divided reference leads the divided VCO in
phase or frequency (fc leads fp), PD_U pulses “low”.
The width of either pulse is directly proportional to
phase offset between the two input signals, fp and
fc.
The phase detector gain is equal to 2.7 V / 2 π,
which numerically yields 0.43 V / radian.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses result
in an increase in VCO frequency; PD_D pulses
result in a decrease in VCO frequency (for a
positive Kv VCO).
A lock detect output, LD is also provided, via the pin
Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
Copyright Peregrine Semiconductor Corp. 2003
Page 12 of 14
File No. 70/0137~01A
|
UTSi CMOS RFIC SOLUTIONS
Free Datasheet http://www.datasheet4u.com/

12 Page





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