ADRF6806 Datasheet PDF - Analog Devices
| Part Number | ADRF6806 | |
| Description | 50 MHz to 525 MHz Quadrature Demodulator | |
| Manufacturers | Analog Devices | |
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Data Sheet
50 MHz to 525 MHz Quadrature
Demodulator with Fractional-N PLL and VCO
ADRF6806
FEATURES
GENERAL DESCRIPTION
IQ demodulator with integrated fractional-N PLL
LO frequency range: 50 MHz to 525 MHz
For the following specifications (LPEN = 0)/(LPEN = 1):
Input P1dB: 12.2 dBm/10.6 dBm
Input IP3: 28.5 dBm/25.2 dBm
Noise figure (DSB): 12.2/11.4
Voltage conversion gain: 1 dB/4.2 dB
Quadrature demodulation accuracy
Phase accuracy: <0.5°
Amplitude accuracy: <0.1 dB
Baseband demodulation: 135 MHz, 3 dB bandwidth
SPI serial interface for PLL programming
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
QAM/QPSK RF/IF demodulators
Cellular W-CDMA/CDMA/CDMA2000
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
The ADRF6806 is a high dynamic range IQ demodulator with
integrated PLL and VCO. The fractional-N PLL/synthesizer
generates a frequency in the range of 2.8 GHz to 4.2 GHz. A
programmable quadrature divider (divide ratio = 4 to 80) divides
the output frequency of the VCO down to the required local
oscillator (LO) frequency to drive the mixers in quadrature.
Additionally, an output divider (divide ratio = 4 to 8) generates
a divided-down VCO signal for external use.
The PLL reference input is supported from 10 MHz to 160 MHz.
The phase detector output controls a charge pump whose output
is integrated in an off-chip loop filter. The loop filter output is
then applied to an integrated VCO.
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
I and Q output paths have excellent quadrature accuracy and
can handle baseband signaling or complex IF up to 120 MHz.
A reduced power mode of operation is also provided by
programming the serial interface registers to reduce current
consumption, with slightly degraded input linearity and output
current drive.
The ADRF6806 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, exposed-paddle,
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.
LON 37
LOP 38
GND 11
DATA 12
CLK 13
LE 14
GND 15
REFIN 6
GND 7
MUXOUT 8
GND VCCLO VCCLO
35 34
17
FUNCTIONAL BLOCK DIAGRAM
LOSEL
36
BUFFER
CTRL
BUFFER
DIV
÷4,
÷6,
÷8
IBBP
33
ADRF6806
IBBN GND
32 31
30 GND
29 DECL3
28 VCCRF
27 GND
SPI
INTERFACE
×2
MUX
÷2
÷4
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
BUFFER
PRESCALER
÷2
MUX
DIVIDER
÷2
TO
÷40
VCO
CORE
TEMP
SENSOR
–
+
PHASE
FREQUENCY
DETECTOR
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
2.5V LDO
VCO LDO
QUAD
÷2
26 RFIN
25 RFIP
24 GND
23 VOCM
22 VCCBB
21 GND
1
VCC1
2
VCC1
34
5
9 10 39 40
16
CPOUT GND RSET DECL2 VCC2 VTUNE DECL1 GND
18 19 20
QBBP QBBN GND
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
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Data Sheet
Parameter
Supply Current (5 V) (LPEN = 1)
Supply Current (5 V)
Supply Current (3.3 V)
Test Conditions/Comments
Normal Rx mode
Rx mode with LO buffer enabled
Power-down mode
Power-down mode
ADRF6806
Min Typ
75
75
10
15
Max Unit
mA
mA
mA
mA
TIMING CHARACTERISTICS
VS1 (VVCCBB and VVCCRF) = 5 V, and VS2 (VVCC1, VVCC2, and VVCCLO) = 3.3 V.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE Setup Time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
CLOCK
t4 t5
DATA
DB23 (MSB)
LE
t1
LE
t2 t3
DB22
DB2
DB1
(CONTROL BIT C2)
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. B | Page 5 of 36
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| Information | Total 30 Pages | |
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