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AD5425 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5425
Beschreibung High Bandwidth Multiplying DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD5425 Datasheet, Funktion
Data Sheet
8-Bit, High Bandwidth
Multiplying DAC with Serial Interface
AD5425
FEATURES
GENERAL DESCRIPTION
2.5 V to 5.5 V supply operation
50 MHz serial interface
2.47 MSPS update rate
INL of ±0.25 LSB
10 MHz multiplying bandwidth
±10 V reference input
Low glitch energy: <2 nV-s
Extended temperature range: −40°C to +125°C
10-lead MSOP package
Guaranteed monotonic
4-quadrant multiplication
Power-on reset with brownout detection
LDAC function
The AD54251 is a CMOS, 8-bit, current output digital-to-analog
converter that operates from a 2.5 V to 5.5 V power supply,
making it suitable for battery-powered applications and many
other applications.
This DAC utilizes a double buffered, 3-wire serial interface that
is compatible with SPI®, QSPI, MICROWIRE, and most DSP
interface standards. An LDAC pin is also provided, which
allows simultaneous updates in a multi-DAC configuration. On
power-up, the internal shift register and latches are filled with
0s and the DAC outputs are 0 V.
As a result of manufacturing on a CMOS submicron process,
0.4 µA typical power consumption
this DAC offers excellent 4-quadrant multiplication charac-
teristics with large signal multiplying bandwidths of 10 MHz.
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor,
RFB, provides temperature tracking and full-scale voltage output
when combined with an external I-to-V precision amplifier.
The AD5425 is available in a small, 10-lead MSOP package.
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
AD5425
8-BIT
R-2R DAC
R
RFB
IOUT1
IOUT2
LDAC
POWER-ON
RESET
DAC REGISTER
INPUT LATCH
SYNC
SCLK
SDIN
CONTROL LOGIC AND
INPUT SHIFT REGISTER
GND
Figure 1.
1 U.S. Patent No. 5,969,657.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/






AD5425 Datasheet, Funktion
Data Sheet
AD5425
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD =2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
fSCLK
t1
t2
t3
t4 2
t5
t6
t7
t8
t9
t10
t11
VDD = 2.5 V to 5.5 V
50
20
8
8
13
5
3
5
30
0
12
10
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
1 Guaranteed by design and characterization, not subject to production test.
2 Falling or rising edge as determined by control bits of serial word.
SCLK
SYNC
DIN
t8 t4
DB7
t6
t5
LDAC1
t1
t2 t3
t7
DB0
t9
t10
LDAC2
NOTES:
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t11
Figure 2. Timing Diagram
Rev. C | Page 5 of 24
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AD5425 pdf, datenblatt
Data Sheet
–60
TA = 25°C
VDD = 3V
–65 VREF = 3.5V p-p
–70
–75
–80
–85
–90
1
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 22. THD and Noise vs. Frequency
20
VDD = 3V
AMPLIFIER = AD8038
0
–20
–40
–60
–80
–100
FULL SCALE
ZERO SCALE
–120
1
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 23. Power Supply Rejection vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
200k
400k
600k
FREQUENCY (Hz)
800k
1M
Figure 24. Wideband SFDR, Clock = 2 MHz, fOUT = 50 kHz
AD5425
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
200k
400k
600k
FREQUENCY (Hz)
800k
1M
Figure 25. Wideband SFDR, Clock = 2 MHz, fOUT = 20 kHz
0
TA = 25°C
–10 VDD = 5V
VREF = 3.5V
–20 AD8038 AMPLIFIER
–30
–40
–50
–60
–70
–80
–90
–100
–110
10k 12k 14k 16k 18k 20k 22k 24k 26k 28k 30k
FREQUENCY (Hz)
Figure 26. Narrowband SFDR, Clock = 2 MHz, fOUT = 20 kHz
0
TA = 25°C
–10 VDD = 5V
VREF = 3.5V
–20 AD8038 AMPLIFIER
–30
–40
–50
–60
–70
–80
–90
–100
–110
25k 30k 35k 40k 45k 50k 55k 60k 65k 70k 75k
FREQUENCY (Hz)
Figure 27. Narrowband SFDR, Clock = 2 MHz, fOUT = 50 kHz
Rev. C | Page 11 of 24
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