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PDF CAT24C512 Data sheet ( Hoja de datos )
| Número de pieza | CAT24C512 | |
| Descripción | 512 kb I2C CMOS Serial EPROM | |
| Fabricantes | ON Semiconductor | |
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CAT24C512
512 Kb I2C CMOS Serial
EEPROM
Description
The CAT24C512 is a 512 Kb Serial CMOS EEPROM, internally
organized as 65,536 words of 8 bits each.
It features a 128−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
External address pins make it possible to address up to eight
CAT24C512 devices on the same bus.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
• Supports Standard, Fast and Fast−Plus I2C Protocol
• 1.8 V to 5.5 V Supply Voltage Range
• 128−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• 8−pin PDIP, SOIC, TSSOP, MSOP, 8−pad UDFN and 8−ball WLCSP
Packages
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
SCL
www.onsemi.com
TSSOP−8
Y SUFFIX
CASE 948AL
UDFN−8
HU5 SUFFIX
CASE 517BU
SOIC−8
W SUFFIX
CASE 751BD
SOIC−8
X SUFFIX
CASE 751BE
PDIP−8
MSOP−8
L SUFFIX
WLCSP−8*
Z SUFFIX
CASE 646AA C8A SUFFIX CASE 846AD
CASE 567JL
* Preliminary. Please contact factory.
PIN CONFIGURATIONS
A0
1
VCC
Pin A1
Reference
A1 WP
A2
SCL
SDA
VCC
VSS
SDA
SCL
PDIP (L), SOIC (W, X),
TSSOP (Y), MSOP (Z)
UDFN (HU5)
(Top View)
A2
VSS
A1
WP
A0
For the location of
Pin 1, please consult
the corresponding
package drawing.
WLCSP (C8A)
(Top View)
A2, A1, A0
WP
CAT24C512
SDA
VSS
Figure 1. Functional Symbol
Pin Name
A0, A1, A2
SDA
SCL
WP
VCC
VSS
PIN FUNCTION
Function
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 7
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
1 Publication Order Number:
CAT24C512/D
1 page  
CAT24C512
Power-On Reset (POR)
The CAT24C512 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
The device will power up into Standby mode after VCC
exceeds the POR trigger level and will power down into
Reset mode when VCC drops below the POR trigger level.
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
signal generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
These pins have on−chip pull−down resistors.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor.
Functional Description
The CAT24C512 supports the Inter−Integrated Circuit
(I2C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C512 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
the bus as determined by the device address inputs A0, A1,
and A2.
I2C Bus Protocol
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when following a
Write command) or sends the Slave into standby mode
(when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 3 bits, A2, A1 and A0, select one of 8 possible Slave
devices. The last bit, R/W, specifies whether a Read (1) or
Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the byte address and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9th clock cycle. If
the Master acknowledges the data, then the Slave continues
transmitting. The Master terminates the session by not
acknowledging the last data byte (NoACK) and by sending
a STOP to the Slave. Bus timing is illustrated in Figure 5.
www.onsemi.com
5
5 Page 
PIN # 1
IDENTIFICATION
TOP VIEW
CAT24C512
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
θ
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.40
0º
NOM
1.27 BSC
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
0.50
1.27
8º
D
A1
A
eb
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
h
θ
L
END VIEW
c
www.onsemi.com
11
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