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ADV8003 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV8003
Beschreibung Video Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 64 Seiten
ADV8003 Datasheet, Funktion
Data Sheet
NatureVue™ Video Signal Processor with
Bitmap OSD, Dual HDMI Tx, and Encoder
ADV8003
FEATURES
Video signal processor
Full 12-bit, 4:4:4 YUV internal processing
Motion adaptive de-interlacing with ultralow angle
interpolation
Multiple video processing paths
Upscaling to 4k × 2k (ADV8003KBCZ-8x models only)
Aspect ratio conversion/panorama scaling
Cadence detection for the recovery of original frames from
film-based content
Dual video scalers enable simultaneous output of multiple
different resolutions
Sharpness and detail enhancement
Noise reduction to reduce random, mosquito, and block
noise
Frame rate converter
Support for up to 3 simultaneous video streams, including
picture-in-picture (PiP) support
On-screen display (OSD)
Internally generated bitmap-based OSD allowing overlay
on one or more video outputs
Overlay on 3D video formats
Dedicated OSD scaler
Alpha blending of OSD data on video data
Disturbance free blending of OSD on either of 2 zones
Option of external OSD
Easy to use software tool for developing OSDs
HDMI transmitters
Dual HDMI transmitters enabling splitter capability
Content type bits
CEC 1.4 controller
Audio return channel (ARC) support
Support of standard S/PDIF for stereo LPCM compressed
audio up to 192 kHz
6-channel uncompressed LPCM I2S audio up to 192 kHz
6-channel direct stream digital (DSD) audio inputs
Noise shaped video (NSV) six-DAC video encoder
Six 12-bit NSV video DACs
Multiformat video output support
Composite (CVBS), S-Video (Y/C), and Component YPrPb
(SD, ED, and HD)
Rovi Rev. 7.1.L1 (SD) and Rev. 1.4 (ED) compliant
Simultaneous SD and ED/HD operation
Professional video mode
Capability to output up to 36-bit TTL data
APPLICATIONS
High-end A/V receivers
Upconverting DVD players/recorders
Blu-ray players/recorders
Set-top boxes
Video conferencing
Standalone video processors
HDMI splitters
TTL DATA
ADV8003
60-BIT
TTL PORT
24-BIT/
36-BIT/
48-BIT
VIDEO
INPUT
36-BIT
VIDEO
OUTPUT
SERIAL VIDEO
FOR EXAMPLE, ADV78500
OUTPUT
SERIAL
VIDEO
RECEIVER
FUNCTIONAL BLOCK DIAGRAM
DDR2 INTERFACE
AUDIO INPUT
LOW ANGLE
PROCESSING
CADENCE
DETECTION
MOTION
DETECTION
CUE
CORRECTION
DE-INTERLACER
DETAIL
ENHANCE
NOISE
REDUCTION
ENHANCE
VIDEO PROCESSING
OSD BUILD
AND SCALE
DUAL SCALER
AND
OSD BLEND
FRC
HDMI Tx1
HDMI Tx2
HD VIDEO
DACs
SD VIDEO
DACs
HDMI
HDMI
HD VIDEO
SD VIDEO
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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ADV8003 Datasheet, Funktion
ADV8003
Data Sheet
SPECIFICATIONS
Measured at DVDD = 1.746 V to 1.854 V, DVDD_DDR = 1.746 V to 1.854 V, PVDD1 = 1.746 V to 1.854 V, PVDD2 = 1.746 V to 1.854 V,
PVDD3 = 1.746 V to 1.854 V, PVDD5 = 1.746 V to 1.854 V, PVDD6 = 1.746 V to 1.854 V, PVDD_DDR = 1.746 V to 1.854 V, AVDD3 =
1.746 V to 1.854 V, CVDD1 = 1.746 V to 1.854 V, AVDD1 = 3.20 V to 3.40 V, AVDD2 = 3.20 V to 3.40 V, DVDD_IO = 3.20 V to 3.40 V,
TMIN to TMAX = 0°C to 70°C, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Table 2.
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity, +ve1
Integral Nonlinearity, −ve1
Differential Nonlinearity, +ve2
Differential Nonlinearity, −ve2
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
DIGITAL INPUTS (5 V TOLERANT)
Input High Voltage
Input Low Voltage
Input Leakage Current
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS3, 4, 5
Digital Power Supply
PLL Analog Supply
PLL Digital Supply
Encoder PLL Supply
HDMI Tx1 PLL Power Supply
HDMI Tx2 PLL Power Supply
HDMI Analog Power Supply
Comparator Power Supply
HDMI Rx Inputs Analog Supply
Encoder Analog Power Supply
Digital Interface Supply
Digital Power Supply Current, Including
DVDD_DDR and PVDD_DDR
PLL Analog Supply Current
PLL Digital Supply Current
Symbol
N
INL
INL
DNL
DNL
VIH
VIL
IIN
CIN
VIH
VIL
IIN
VOH
VOL
ILEAK
COUT
DVDD
PVDD1
PVDD2
PVDD3
PVDD5
PVDD6
AVDD3
CVDD1
AVDD1
AVDD2
DVDD_IO
IDVDD
IPVDD1
IPVDD2
Test Conditions/Comments
DAC outputs sampled at 500 kHz
DAC outputs sampled at 500 kHz
DAC outputs sampled at 500 kHz
DAC outputs sampled at 500 kHz
HEAC inputs
DDR_DQS inputs
Other digital inputs
Mode 1
Mode 2
Power-down mode
Mode 1
Mode 2
Power-down mode
Mode 1
Mode 2
Power-down mode
Min
Typ Max
Unit
12
0.389
−0.322
0.183
−0.208
Bits
LSB
LSB
LSB
LSB
0.7 ×
DVDD_IO
13
V
0.3 ×
DVDD_IO
±60
±60
±10
V
µA
µA
µA
pF
3.4 V
0.8 V
±60 µA
2.4 V
0.4 V
±10 µA
13 pF
1.746
1.746
1.746
1.746
1.746
1.746
1.746
1.746
3.20
3.20
3.20
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
3.3
3.3
3.3
1989.0
1423.0
60.6
23.0
21.0
1.3
21.8
19.9
0.2
1.854
1.854
1.854
1.854
1.854
1.854
1.854
1.854
3.40
3.40
3.40
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. B | Page 6 of 64
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ADV8003 pdf, datenblatt
ADV8003
Data Sheet
SPI CS2
MODE CPOL CPHA
0 0 0 SCK2
1 0 1 SCK2
2 1 0 SCK2
3 1 1 SCK2
t9
t10
t13
t11
t12
MOSI2
MISO2
INSTRUCTION(0x0B) 24-BIT ADDRESS
DUMMY BYTE
23 22 21 ... 3 2 1 0 7 6 5 4 3 2 1 0
DATA OUT 1
DATA OUT 2
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
Figure 5. Detailed SPI Master Timing Diagram (Serial Port 2)
SCK2
t14
t15
t16
t17 t17
t18
MOSI2
CS2
MISO2
(FALLING EDGE CAPTURE)
MISO2
(RISING EDGE CAPTURE)
Figure 6. Serial Port 2 Master Mode Timing (SPI Mode 0 and SPI Mode 3)
t18
SCK2
MOSI2
CS2
MISO2
(RISING EDGE CAPTURE)
MISO2
(FALLING EDGE CAPTURE)
t14 t19
t20
t21 t21
t22 t22
Figure 7. Serial Port 2 Master Mode Timing (SPI Mode 1 and SPI Mode 2)
Rev. B | Page 12 of 64
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12 Page





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