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PDF ADG5421 Data sheet ( Hoja de datos )
| Número de pieza | ADG5421 | |
| Descripción | (ADG5421 / ADG5423) Dual SPST Switches | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Latch-up immune under all circumstances
Human body model (HBM) ESD rating: 8 kV
Low on resistance: 13.5 Ω
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VDD to VSS analog signal range
APPLICATIONS
High voltage signal routing
Automatic test equipment
Analog front-end circuits
Precision data acquisition
Industrial instrumentation
Amplifier gain select
Relay replacement
GENERAL DESCRIPTION
The ADG5421/ADG5423 are monolithic industrial,
complementary metal oxide semiconductor (CMOS) analog
switches containing two independent latch-up immune single-
pole/single-throw (SPST) switches. Each switch conducts
equally well in both directions when on, and has an input signal
range that extends to the power supplies. In the off condition,
signal levels up to the supplies are blocked. Both ADG5421
switches are turned on with a Logic 1 input, whereas the
ADG5423 has one switch turned on and one switch turned off
for a Logic 1 input. The ADG5423 exhibits break-before-make
action for use in multiplexer applications.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications where low distortion is critical. The
latch-up immune construction and high ESD rating make these
switches more robust in harsh environments.
High Voltage Latch-Up Proof,
Dual SPST Switches
ADG5421/ADG5423
FUNCTIONAL BLOCK DIAGRAMS
ADG5421
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 1. ADG5421
ADG5423
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 2. ADG5423
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench
separates the P channel and N channel transistors, thereby
preventing latch-up even under severe overvoltage
conditions.
2. Low RON of 13.5 Ω.
3. Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5421/ADG5423 can operate
from dual supplies up to ±22 V.
4. Single-supply operation. For applications where the analog
signal is unipolar, the ADG5421/ADG5423 can operate from
a single-rail power supply up to 40 V.
5. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
6. No VL logic power supply required.
7. Available in 10-lead MSOP package.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
ADG5421/ADG5423
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
25°C
26
−40°C to +85°C
−40°C to +125°C
0 V to VDD
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
30 38
0.1
1 1.5
5.5
6.8 8.3
±0.05
44
1.6
12.3
Drain Off Leakage, ID (Off)
±0.25
±0.05
±1
±10
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
tOFF
Break-Before-Make Time Delay, tD
(ADG5423 Only)
Charge Injection, QINJ
±0.25
±0.1
±0.4
±1
±4
0.002
6
295
370 470
192
235 273
142
55
±10
±20
2.0
0.8
±0.1
540
295
78
Off Isolation
−55
Channel-to-Channel Crosstalk
−85
Total Harmonic Distortion + Noise
0.03
−3 dB Bandwidth
Insertion Loss
290
−1.7
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
VDD
14
15
38
40
50
1 Guaranteed by design; not subject to production test.
65
9/40
Rev. 0 | Page 5 of 20
Unit Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 0 V to 10 V, IS = −10 mA; see
Figure 24
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VDD = +13.2 V, VSS = 0 V
VS = 1 V to 10 V, VD = 10 V to 1 V; see
Figure 23
VS = 1 V to 10 V, VD = 10 V to 1 V; see
Figure 23
VS = VD = 1 V to 10 V; see Figure 22
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
µA typ
µA max
V min/V max
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 31
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 28
RL = 1 kΩ, 6 V p-p, f = 20 Hz to
20 kHz; see Figure 26
RL = 50 Ω, CL = 5 pF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 27
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
Free Datasheet http://www.datasheet4u.com/
5 Page 
Data Sheet
40
35
30 TA = +125°C
25 TA = +85°C
20 TA = +25°C
15 TA = –40°C
10
5
VVDSSD
=
=
12V
0V
0
0 2 4 6 8 10 12
VS, VD (V)
Figure 10. On Resistance as a Function of VS (VD) for Different Temperatures,
12 V Single Supply
25
VVDSSD
=
=
36V
0V
20
15 TA = +125°C
TA = +85°C
10 TA = +25°C
TA = –40°C
5
0
0 5 10 15 20 25 30 35 40
VS, VD (V)
Figure 11. On Resistance as a Function of VS (VD) for Different Temperatures,
36 V Single Supply
0.6
VVVDSBSDIA=S=
+15V
–15V
= +10V/–10V
0.4
0.2
ID, IS (ON) + +
IS (OFF) + –
ID (OFF) – +
ID, IS (ON) – –
0
–0.2 IS (OFF) – +
ID (OFF) + –
–0.4
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 12. Leakage Currents as a Function of Temperature, ±15 V Dual Supply
ADG5421/ADG5423
0.4
VVVDSBSDIA=S=
+20V
–20V
= +15V/–15V
0.2
0
ID, IS (ON) + +
IS (OFF) + –
ID (OFF) – +
–0.2
ID, IS (ON) – –
IS (OFF) – +
–0.4
ID (OFF) + –
–0.6
0
25 50 75 100
TEMPERATURE (°C)
125
Figure 13. Leakage Currents as a Function of Temperature,
±20 V Dual Supply
0.4
VVVDSBSDIA=S=
12V
0V
= 1V/10V
0.3
0.2
0.1
ID, IS (ON) + +
ID, IS (ON) – –
IS (OFF) + –
0
–0.1
–0.2
0
ID (OFF) – +
IS (OFF) – +
ID (OFF) + –
25 50 75 100 125
TEMPERATURE (°C)
Figure 14. Leakage Currents as a Function of Temperature,
12 V Single Supply
0.4
VVVDSBSDIA=S=
36V
0V
= 1V/30V
0.2
ID, IS (ON) + +
IS (OFF) + –
0
ID (OFF) – +
–0.2
ID, IS (ON) – –
IS (OFF) – +
–0.4
ID (OFF) + –
–0.6
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 15. Leakage Currents as a Function of Temperature,
36 V Single Supply
Rev. 0 | Page 11 of 20
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11 Page | ||
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| PDF Descargar | [ Datasheet ADG5421.PDF ] | |
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