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PDF ADG5434 Data sheet ( Hoja de datos )
| Número de pieza | ADG5434 | |
| Descripción | (ADG5433 / ADG5434) Triple/Quad SPDT Switches | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Latch-up proof
Human body model (HBM) ESD rating: 8 kV
Low on resistance (13.5 Ω)
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS to VDD analog signal range
APPLICATIONS
Relay replacement
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
GENERAL DESCRIPTION
The ADG5433 and ADG5434 are monolithic industrial CMOS
analog switches comprising three independently selectable
single-pole, double-throw (SPDT) switches and four indepen-
dently selectable SPDT switches, respectively.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An EN
input on the ADG5433 (LFCSP and TSSOP packages) is used to
enable or disable the device. When disabled, all channels are
switched off.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications, where low distortion is critical.
High Voltage Latch-Up Proof,
Triple/Quad SPDT Switches
ADG5433/ADG5434
FUNCTIONAL BLOCK DIAGRAMS
ADG5433
S1A
D1
S1B
S3B
D3
S2B S3A
D2
S2A
LOGIC
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR
A LOGIC 1 INPUT.
Figure 1. ADG5433 TSSOP and LFCSP_WQ
ADG5434
S1A S4A
D1 D4
S1B S4B
S2B S3B
D2 D3
S2A S3A
LOGIC
IN1 IN2 IN3 IN4
SWITCHES SHOWN FOR
A LOGIC 1 INPUT.
Figure 2. ADG5434 TSSOP
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench
separates the P and N channel transistors thereby preventing
latch-up even under severe overvoltage conditions.
2. Low RON.
3. Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5433/ADG5434 can be operated
from dual supplies up to ±22 V.
4. Single-supply operation. For applications where the analog
signal is unipolar, the ADG5433/ADG5434 can be operated
from a single-rail power supply up to 40 V.
5. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
6. No VL logic power supply required.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
ADG5433/ADG5434
Parameter
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
ISS
VDD/VSS
25°C
0.012
140
−0.8
15
23
52
50
70
0.001
−40°C to +85°C
−40°C to +125°C
110
1
±9/±22
Unit
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
µA typ
µA max
µA typ
µA max
V min/V max
Test Conditions/Comments
RL = 1 kΩ, 20 V p-p, f = 20 Hz to
20 kHz; see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
25°C −40°C to +85°C −40°C to +125°C Unit
0 V to VDD
V
26 Ω typ
On-Resistance Match Between Channels,
∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
30
0.3
1
5.5
6.5
±0.05
36
1.5
8
42
1.6
12
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
Drain Off Leakage, ID (Off )
±0.25 ±1
±0.1
±7
nA max
nA typ
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
±0.4 ±4
±0.1
±0.4 ±4
0.002
6
220
290 357
228
289 370
90
115 131
±30
±30
2.0
0.8
±0.1
400
426
151
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
Test Conditions/Comments
VS = 0 V to 10 V, IS = −10 mA; see
Figure 26
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 29
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 29
VS = VD = 1 V/10 V; see Figure 25
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 8 V
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 34
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 34
Rev. B | Page 5 of 24
Free Datasheet http://www.datasheet4u.com/
5 Page 
Data Sheet
ADG5433/ADG5434
IN1 1
20 IN4
S1A 2
19 S4A
D1 3
18 D4
S1B 4
VSS 5
GND 6
S2B 7
ADG5434
TOP VIEW
(Not to Scale)
17 S4B
16 VDD
15 NC
14 S3B
D2 8
13 D3
S2A 9
12 S3A
IN2 10
11 IN3
NC = NO CONNECT
Figure 5. ADG5434 TSSOP Pin Configuration
Table 10. ADG5434 Pin Function Descriptions
Pin No.
Mnemonic Description
1 IN1 Logic Control Input 1.
2 S1A Source Terminal 1A. This pin can be an input or an output.
3 D1 Drain Terminal 1. This pin can be an input or an output.
4 S1B Source Terminal 1B. This pin can be an input or an output.
5 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to
ground.
6 GND Ground (0 V) Reference.
7 S2B Source Terminal 2B. This pin can be an input or an output.
8 D2 Drain Terminal 2. This pin can be an input or an output.
9 S2A Source Terminal 2A. This pin can be an input or an output.
10 IN2 Logic Control Input 2.
11 IN3 Logic Control Input 3.
12 S3A Source Terminal 3A. This pin can be an input or an output.
13 D3 Drain Terminal 3. This pin can be an input or an output.
14 S3B Source Terminal 3B. This pin can be an input or an output.
15 NC No Connect.
16 VDD Most Positive Power Supply Potential.
17 S4B Source Terminal 4B. This pin can be an input or an output.
18 D4 Drain Terminal 4. This pin can be an input or an output.
19 S4A Source Terminal 4A. This pin can be an input or an output.
20 IN4 Logic Control Input 4.
Table 11. ADG5434 Truth Table
INx
0
1
SxA
Off
On
SxB
On
Off
Rev. 0 | Page 11 of 24
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11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADG5434.PDF ] | |
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