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AD9649 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9649
Beschreibung 1.8V Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9649 Datasheet, Funktion
Data Sheet
14-Bit, 20/40/65/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9649
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
74.3 dBFS at 9.7 MHz input
71.5 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
45 mW at 20 MSPS
87 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.35 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Integer 1, 2, or 4 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out (DCO) with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
RBIAS
VCM
VIN+
VIN–
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND SDIO SCLK CSB DRVDD
SPI
PROGRAMMING DATA
ADC
CORE
OR
D13 (MSB)
D0 (LSB)
DCO
REF
SELECT
DIVIDE BY
1, 2, 4
AD9649
MODE
CONTROLS
CLK+ CLK–
PDWN DFS MODE
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD9649 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The sample-and-hold circuit maintains excellent performance
for input frequencies up to 200 MHz and is designed for low
cost, low power, and ease of use.
3. A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO, data output
(D13 to D0) timing and offset adjustments, and voltage
reference modes.
4. The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP
that is pin compatible with the AD9629 12-bit ADC and
the AD9609 10-bit ADC, enabling a simple migration path
between 10-bit and 14-bit converters sampling from 20 MSPS
to 80 MSPS.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9649 Datasheet, Funktion
Data Sheet
AD9649
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
TWO-TONE SFDR
fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)
ANALOG INPUT BANDWIDTH
AD9649-20/AD9649-40
AD9649-65
AD9649-80
Temp Min Typ
Max Min Typ Max Min Typ Max Unit
25°C
25°C
Full 73.1
25°C
Full
25°C
74.7
74.4
73.7
71.5
74.5
74.3
73.6
73.7
71.5
74.3
74.1
73.6
72.7
71.5
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
Full 73.0
25°C
Full
25°C
74.6
74.3
73.6
70.0
74.4
74.2
73.5
73.6
70.0
74.1
74.0
73.5
72.6
70.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C 12.0
25°C 12.0
25°C 11.9
25°C 11.3
12.0 12.0 Bits
12.0 12.0 Bits
11.9 11.9 Bits
11.3 11.3 Bits
25°C −95
−95 −93 dBc
25°C −95
−95 −93 dBc
Full −82 −83
dBc
25°C −94
−94 −92 dBc
Full −82 dBc
25°C −80
−80 −80 dBc
25°C
25°C
Full 82
25°C
Full
25°C
95
94
93
80
95
94
83
93
80
93
93
92
82
80
dBc
dBc
dBc
dBc
dBc
dBc
25°C −100
−100
−100
dBc
25°C −100
−100
−100
dBc
Full −90 −90
dBc
25°C −100
−100
−100
dBc
Full −90 dBc
25°C −95
−95 −95 dBc
25°C 90
25°C 700
90 90 dBc
700 700 MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. A | Page 5 of 32

6 Page









AD9649 pdf, datenblatt
Data Sheet
AD9649
TYPICAL PERFORMANCE CHARACTERISTICS
AD9649-80
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle
clock, unless otherwise noted.
00
80MSPS
80MSPS
–15
9.7MHz @ –1dBFS
SNR = 73.4dB (74.4dBFS)
30.5MHz @ –1dBFS
–15 SNR = 73.2dB (74.2dBFS)
SFDR = 94.4dBc
SFDR = 93.6dBc
–30 –30
–45 –45
–60 –60
–75 –75
–90
–105
26
3
5
4
–90
–105
3
5
26
4
–120
4 8 12 16 20 24 28 32 36
FREQUENCY (MHz)
–120
4 8 12 16 20 24 28 32 36
FREQUENCY (MHz)
Figure 4. AD9649-80 Single-Tone FFT with fIN = 9.7 MHz
Figure 7. AD9649-80 Single-Tone FFT with fIN = 30.5 MHz
0
80MSPS
70.3MHz @ –1dBFS
–15 SNR = 72.1dB (73.1dBFS)
SFDR = 93.5dBc
–30
–45
–60
–75
–90
–105
2
6
3
5
4
–120
4 8 12 16 20 24 28 32 36
FREQUENCY (MHz)
Figure 5. AD9649-80 Single-Tone FFT with fIN = 70.3 MHz
0
80MSPS
200MHz @ –1dBFS
–15 SNR = 70.5dB (71.5dBFS)
SFDR = 80.2dBc
–30
–45
–60
–75
2
–90
–105 4 6
3
5
–120
4 8 12 16 20 24 28 32 36
FREQUENCY (MHz)
Figure 8. AD9649-80 Single-Tone FFT with fIN = 200 MHz
0
80MSPS
30.5MHz @ –7dBFS
–15 32.5MHz @ –7dBFS
SFDR = 89.5dBc (96.5dBFS)
–30
–45
–60
–75
–90
–105
F2 – F1
2F1 + F2
2F2 + F1
F1 + F2
2F2 – F1 2F1 – F2
–120
4 8 12 16 20 24 28 32 36
FREQUENCY (MHz)
Figure 6. AD9649-80 Two-Tone FFT with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz
0
–20
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
–100
SFDR (dBFS)
IMD3 (dBFS)
–120
–90
–78 –66 –54 –42 –30 –18
INPUT AMPLITUDE (dBFS)
–6
Figure 9. AD9649-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz
Rev. A | Page 11 of 32

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