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AD9608 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9608
Beschreibung 1.8V Dual Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9608 Datasheet, Funktion
FEATURES
1.8 V analog supply operation
1.8 V CMOS or 1.8 V LVDS output
SNR = 61.7 dBFS at 70 MHz
SFDR = 85 dBc at 70 MHz
Low power: 71 mW/channel ADC core at 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.13 LSB
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
I/Q demodulation systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
10-Bit, 125/105 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9608
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
SDIO SCLK CSB
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
SPI
ADC
PROGRAMMING DATA
AD9608
ADC
DIVIDE DUTY CYCLE
1 TO 8 STABILIZER
MODE
CONTROLS
ORA
D9A
D0A
DCOA
DRVDD
ORB
D9B
D0B
DCOB
CLK+ CLK–
SYNC
DCS
PDWN DFS OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
1. Operates from a single 1.8 V analog power supply and
features a separate digital output driver supply to accom-
modate 1.8 V CMOS or 1.8 V LVDS logic families.
2. Provides a patented sample-and-hold circuit that maintains
excellent performance for input frequencies up to 200 MHz
and is designed for low cost, low power, and ease of use.1
3. Includes a standard serial port interface that supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing,
and offset adjustments.
4. Packaged in a 64-lead, RoHS-compliant LFCSP that is pin
compatible with the AD9650, AD9269, and AD9268 16-bit
ADCs, the AD9258 and AD9648 14-bit ADCs, the AD9628
and AD9231 12-bit ADCs, and the AD9204 10-bit ADC,
enabling a simple migration path between 10-bit and 16-bit
converters sampling from 20 MSPS to 125 MSPS.
1 This product is protected by a U.S. patent.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/






AD9608 Datasheet, Funktion
AD9608
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS/SYNC)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO/DCS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (OEB, PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
Temp Min Typ Max
CMOS/LVDS/LVPECL
Full 0.9
Full 0.3
3.6
Full AGND − 0.3
AVDD + 0.2
Full 0.9
1.4
Full −10
+10
Full −10
+10
Full 4
Full 8
10 12
Full 1.22
Full 0
Full −10
Full 40
Full
Full
26
2
DRVDD + 0.2
0.6
+10
132
Full 1.22
Full 0
Full −92
Full −10
Full
Full
26
2
DRVDD + 0.2
0.6
−135
+10
Full 1.22
Full 0
Full −10
Full 38
Full
Full
26
5
DRVDD + 0.2
0.6
+10
128
Full 1.22
Full 0
Full −90
Full −10
Full
Full
26
5
DRVDD + 0.2
0.6
−134
+10
Unit
V
V p-p
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
Full 1.79
Full 1.75
Full
Full
V
V
0.2 V
0.05 V
Rev. 0 | Page 6 of 40
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6 Page









AD9608 pdf, datenblatt
AD9608
Pin No.
Mnemonic
Digital Input
3 SYNC
Digital Outputs
32 D0A (LSB)
33 D1A
34 D2A
35 D3A
36 D4A
38 D5A
39 D6A
40 D7A
41 D8A
42 D9A (MSB)
43 ORA
11 D0B (LSB)
12 D1B
13 D2B
14 D3B
15 D4B
16 D5B
17 D6B
18 D7B
20 D8B
21 D9B (MSB)
22 ORB
24 DCOA
23 DCOB
SPI Control
45 SCLK/DFS
44 SDIO/DCS
46 CSB
ADC Configuration
47 OEB
48 PDWN
Type
Description
Input
Digital Synchronization Pin. Slave mode only.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A Overrange Output.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B Overrange Output
Channel A Data Clock Output.
Channel B Data Clock Output.
Input
Input/Output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
Input
Input
Output Enable Input (Active Low). Pin must be enabled via SPI.
Power-Down Input in External Pin Mode. In SPI mode, this input can be configured
as power-down or standby.
Rev. 0 | Page 12 of 40
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12 Page





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