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PDF AD9524 Data sheet ( Hoja de datos )
| Número de pieza | AD9524 | |
| Descripción | Jitter Cleaner and Clock Generator | |
| Fabricantes | Analog Devices | |
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Data Sheet
Jitter Cleaner and Clock Generator with
6 Differential or 13 LVCMOS Outputs
AD9524
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <±150 ps
6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
6 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <±50 ps
Duty-cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <200 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Distribution phase noise floor: −160 dBc/Hz
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate up to 130 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate of up to 259 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
FUNCTIONAL BLOCK DIAGRAM
REFA,
REFA
REFB,
REFB
REF_TEST
OSC
PLL1
PLL2
AD9524
OUT0,
OUT0
OUT1,
OUT1
SCLK/SCL
SDIO/SDA
SDO
CONTROL
INTERFACE
(SPI AND I2C)
ZERO
DELAY
EEPROM
6-CLOCK
DISTRIBUTION
OUT4,
OUT4
OUT5,
OUT5
ZD_IN, ZD_IN
Figure 1.
GENERAL DESCRIPTION
The AD9524 provides a low power, multi-output, clock
distribution function with low jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to
4.0 GHz.
The AD9524 is defined to support the clock requirements for
long term evolution (LTE) and multicarrier GSM base station
designs. It relies on an external VCXO to provide the reference
jitter cleanup to achieve the restrictive low phase noise require-
ments necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates six low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free coarse timing adjustment in
increments that are equal to one-half the period of the signal
coming out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user defined register settings for power-up and
chip reset.
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9524
Data Sheet
SPECIFICATIONS
fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 3932.16 MHz, doubler is off, channel control
low power mode off, divider phase =1, unless otherwise noted. Typical is given for VDD = 3.3 V ± 5%, and TA = 25°C, unless otherwise
noted. Minimum and maximum values are given over the full VDD and TA (−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
Min Typ Max
SUPPLY VOLTAGE
VDD3_PLL1, Supply Voltage for PLL1
3.3
VDD3_PLL2, Supply Voltage for PLL2
3.3
VDD3_REF, Supply Voltage Clock Output Drivers Reference
3.3
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
3.3
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
1.8
TEMPERATURE
Ambient Temperature Range, TA
−40 +25 +85
Junction Temperature, TJ
115
Unit Test Conditions/Comments
V 3.3 V ± 5%
V 3.3 V ± 5%
V 3.3 V ± 5%
V 3.3 V ± 5%
V 1.8 V ± 5%
°C
°C
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 41 and Pin 40,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 38 and Pin 37, respectively).
SUPPLY CURRENT
Table 2.
Parameter
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL1, Supply Voltage for PLL1
VDD3_PLL2, Supply Voltage for PLL2
VDD3_REF, Supply Voltage Clock Output Drivers
Reference
LVPECL Mode
Min Typ Max
37 43
67 77.7
56
LVDS Mode
4 4.8
HSTL Mode
3 3.6
CMOS Mode
3 3.6
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers2
CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVPECL Compatible Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
3.5 4.2
11.5 13.2
40 45
6.5 7.5
23 26.3
13 14.4
41 46.5
14 16.3
2 2.4
Rev. F | Page 4 of 56
Unit Test Conditions/Comments
mA Decreases by 9 mA typical if REFB is turned
off
mA
mA Only one output driver turned on; for each
additional output that is turned on, the current
increments by 1.2 mA maximum
mA Only one output driver turned on; for each
additional output that is turned on, the current
increments by 1.2 mA maximum
mA Values are independent of the number of
outputs turned on
mA Values are independent of the number of
outputs turned on
mA Current for each divider: f = 245.76 MHz
Channel x control register, Bit 4 = 0
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 15.36 MHz, 10 pF load
5 Page 
AD9524
Data Sheet
LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL
Table 13.
Parameter
VOLTAGE
Input High
Input Low
INPUT LOW CURRENT
Min
2.0
CAPACITANCE
RESET TIMING
Pulse Width Low
Inactive to Start of Register Programming
SYNC TIMING
Pulse Width Low
50
100
1.5
Typ Max
0.8
±80 ±250
3
Unit Test Conditions/Comments
V
V
µA The minus sign indicates that, due to the
internal pull-up resistor, current is flowing
out of the AD9524
pF
ns
ns
ns High speed clock is CLK input signal
STATUS OUTPUT PINS—STATUS1, STATUS0
Table 14.
Parameter
VOLTAGE
Output High
Output Low
Min
2.94
Typ Max
0.4
Unit Test Conditions/Comments
V
V
SERIAL CONTROL PORT—SPI MODE
Table 15.
Parameter
CS (INPUT)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Min
Input Capacitance
SCLK (INPUT) IN SPI MODE
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
Typ Max
2.0
0.8
30
−110
2
2.0
0.8
240
1
2
Unit Test Conditions/Comments
CS has an internal 40 kΩ pull-up resistor
V
V
µA
µA The minus sign indicates that, due to the
internal pull-up resistor, current is flowing out
of the AD9524
pF
SCLK has an internal 40 kΩ pull-down resistor
in SPI mode but not in I2C mode
V
V
µA
µA
pF
2.0
0.8
1
1
2
Rev. F | Page 10 of 56
V
V
µA
µA
pF
11 Page | ||
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| PDF Descargar | [ Datasheet AD9524.PDF ] | |
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