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PDF AD5669R Data sheet ( Hoja de datos )
| Número de pieza | AD5669R | |
| Descripción | (AD5629R / AD5669R) Octal / 12-/16-Bit / I2C / denseDACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Octal, 12-/16-Bit, I2C, denseDACs
with 5 ppm/°C On-Chip Reference
AD5629R/AD5669R
FEATURES
Low power octal DACs
AD5629R: 12 bits
AD5669R: 16 bits
2.6 mm × 2.6 mm 16-ball WLCSP
4 mm × 4 mm 16-lead LFCSP and 16-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA at 5 V, 200 nA at 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware LDACE and CLRE functions
A A AA
I2C-compatible serial interface supports standard (100 kHz)
and fast (400 kHz) modes
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
GENERAL DESCRIPTION
The AD5629R/AD5669R devices are low power, octal, 12-/16-
bit, buffered voltage-output DACs. All devices are guaranteed
monotonic by design.
The AD5629R/AD5669R have an on-chip reference with an
internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V,
5 ppm/°C reference, giving a full-scale output range of 2.5 V.
The AD5629R-2/AD5629R-3 and the AD5669R-2/AD5669R-3
have a 2.5 V 5 ppm/°C reference, giving a full-scale output range
of 5 V depending on the option selected. Devices with 1.25 V
reference selected operate from a single 2.7 V to 5.5 V supply.
Devices with 2.5 V reference selected operate from 4.5 V to 5.5 V.
The on-chip reference is off at power-up, allowing the use of an
external reference. The internal reference is enabled via a
software write.
SCL
SDA
A0
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFIN/VREFOUT
AD5629R/AD5669R
LDAC
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
1.25V/2.5V REF
BUFFER
STRING
DAC A
BUFFER
STRING
DAC B
BUFFER
STRING
DAC C
BUFFER
STRING
DAC D
BUFFER
STRING
DAC E
BUFFER
STRING
DAC F
BUFFER
STRING
DAC G
BUFFER
STRING
DAC H
POWER-ON RESET
POWER-DOWN LOGIC
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
LDAC CLR
Figure 1.
GND
The parts incorporate a power-on reset circuit to ensure that the
DAC output powers up to 0 V (AD5629R-1/AD5629R-2,
AD5669R-1/AD5669R-2) or midscale (AD5629R-3/AD5669R-3)
and remains powered up at this level until a valid write takes
place. The part contains a power-down feature that reduces the
current consumption of the device to 400 nA at 5 V and
provides software-selectable output loads while in power-down
mode for any or all DAC channels.
PRODUCT HIGHLIGHTS
1. Octal, 12-/16-bit DACs.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 16-lead LFCSP and TSSOP, and 16-ball
WLCSP.
4. Power-on reset to 0 V or midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
AD5629R/AD5669R
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 2
AD5629R
Resolution
Relative Accuracy
Differential Nonlinearity
AD5669R
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
DC Crosstalk
(Internal Reference)
OUTPUT CHARACTERISTICS 3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
AD5629R/AD5669R
Reference Tempco3
Reference Output Impedance
LOGIC INPUTS3
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
A Grade 1
Min Typ Max
12
±0.5 ±4
±0.25
16
±8 ±32
±1
6 19
±2
−0.2 −1
±1
±2.5
±6 ±19
–80
10
5
10
25
10
0 VDD
2
10
0.5
30
4
40 50
0 VDD
14.6
1.247
1.253
±15
7.5
±3
0.8
2
3
B Grade1
Min Typ Max
12
±0.5 ±1
±0.25
16
±8 ±16
±1
6 19
±2
−0.2 −1
±1
±2.5
±6 ±19
–80
10
5
10
25
10
0 VDD
2
10
0.5
30
4
40 50
0 VDD
14.6
1.247
±5
±15
7.5
1.253
±15
±3
0.8
2
3
Unit
Bits
LSB
LSB
Bits
LSB
LSB
mV
µV/°C
% FSR
% FSR
ppm
mV
dB
µV
µV/mA
µV
µV
µV/mA
V
nF
nF
Ω
mA
µs
µA
kΩ
V
ppm/°C
kΩ
µA
V
V
pF
Conditions/Comments
See Figure 6
Guaranteed monotonic by design (see Figure 8)
See Figure 5
Guaranteed monotonic by design (see Figure 7)
All 0s loaded to DAC register (see Figure 18)
All 1s loaded to DAC register (see Figure 19)
Of FSR/°C
VDD ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
RL = ∞
RL = 2 kΩ
VDD = 3 V
Coming out of power-down mode, VDD = 3 V
VREFIN = VDD = 3.6 V (per DAC channel)
TA = 25°C
LFCSP, TSSOP
WLCSP
All digital inputs
VDD = 3 V
VDD = 3 V
Rev. B | Page 5 of 32
Free Datasheet http://www.datasheet4u.com/
5 Page 
Data Sheet
AD5629R/AD5669R
Table 6. Pin Function Descriptions
Pin No.
LFCSP TSSOP WLCSP Mnemonic
15 1 B2 LDAC
16 2
13
24
35
46
57
68
A4 A0
B3 VDD
B4 VOUTA
B1 VOUTC
C4 VOUTE
C2 VOUTG
D3 VREFIN/VREFOUT
79
D2 CLR
8 10
9 11
10 12
11 13
12 14
13 15
C3
C1
D4
D1
A1
A3
VOUTH
VOUTF
VOUTD
VOUTB
GND
SDA
14 16
A4
SCL
17 N/A N/A Exposed Pad
(EPAD)
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers
have new data. This allows all DAC outputs to simultaneously update. Alternatively,
this pin can be tied permanently low.
Address Input. Sets the least significant bit of the 7-bit slave address.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the
supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
The AD5629R/AD5669R have a common pin for reference input and reference
output. When using the internal reference, this is the reference output pin. When
using an external reference, this is the reference input pin. The default for this pin is
as a reference input.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all
LDAC pulses are ignored. When CLR is activated, the input register and the DAC
register are updated with the data contained in the CLR code register—zero scale,
midscale, or full scale. The default setting clears the output to 0 V.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Parts.
Serial Data Input. This is used in conjunction with the SCL line to clock data into or
out of the 32-bit input shift register. It is a bidirectional, open-drain data line that
should be pulled to the supply with an external pull-up resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or
out of the 32-bit input shift register.
The exposed pad must be tied to GND.
Rev. B | Page 11 of 32
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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| PDF Descargar | [ Datasheet AD5669R.PDF ] | |
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