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PDF AD7690 Data sheet ( Hoja de datos )

Número de pieza AD7690
Descripción Differential ADC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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No Preview Available ! AD7690 Hoja de datos, Descripción, Manual

18-Bit, 1.5 LSB INL, 400 kSPS PulSAR®
Differential ADC in MSOP/QFN
AD7690
FEATURES
18-bit resolution with no missing codes
Throughput: 400 kSPS
INL: ±0.75 LSB typ, ±1.5 LSB max (±6 ppm of FSR)
Dynamic range: 102 dB @ 400 kSPS
Oversampled dynamic range: 125 dB @ 1 kSPS
Noise-free code resolution: 20 bits @ 1 kSPS
Effective resolution: 22.7 bits @ 1 kSPS
SINAD: 101.5 dB @ 1 kHz
THD: −125 dB @ 1 kHz
True differential analog input range: ±VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface, SPI®/QSPI™/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs and busy indicator
Power dissipation
4.25 μW @ 100 SPS
4.25 mW @ 100 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin compatible with QFN/MSOP PulSAR ADCs
APPLICATIONS
Battery-powered equipment
Data acquisition
Seismic data acquisition systems
DVMs
Instrumentation
Medical instruments
1.5
POSITIVE INL = +0.42LSB
NEGATIVE INL = –0.6LSB
1.0
0.5
0
–0.5
–1.0
–1.5
0
65536
131072
196608
CODE
Figure 1. Integral Nonlinearity vs. Code
262144
APPLICATION EXAMPLE
+2.5V TO +5V +5V
±10V, ±5V, ...
ADA4941-1
REF VDD VIO
IN+ SDI
SCK
IN–
GND
SDO
CNV
AD7690
Figure 2.
+1.8V TO VDD
3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)
Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
Type
100
kSPS
250
kSPS
400 kSPS
to
500 kSPS
18-Bit True
Differential
AD7691 AD7690
AD7982
16-Bit True
AD7684 AD7687 AD7688
Differential
AD7693
16-Bit Pseudo AD7680 AD7685 AD7686
Differential AD7683 AD7694
14-Bit Pseudo AD7940 AD7942 AD7946
Differential
1000
kSPS
AD7982
AD7980
ADC
Driver
ADA4941
ADA4841
ADA4941
ADA4841
ADA4841
ADA4841
GENERAL DESCRIPTION
The AD7690 is an 18-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 18-bit sampling ADC
with no missing codes, an internal conversion clock, and a
versatile serial interface port. On the CNV rising edge, it
samples the voltage difference between the IN+ and IN− pins.
The voltages on these pins swing in opposite phase between 0 V
and REF. The reference voltage, REF, is applied externally and
can be set up to the supply voltage.
The power of the AD7690 scales linearly with the throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.
The AD7690 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/

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AD7690 pdf
AD7690
TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4. 1
Parameter
Symbol Min Typ Max
Conversion Time: CNV Rising Edge to Data Available
tCONV
0.5
2.1
Acquisition Time
tACQ 400
Time Between Conversions
tCYC 2.5
CNV Pulse Width (CS Mode)
tCNVH
10
SCK Period (CS Mode)
tSCK 15
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
17
VIO Above 3 V
18
VIO Above 2.7 V
19
VIO Above 2.3 V
20
SCK Low Time
tSCKL
7
SCK High Time
tSCKH
7
SCK Falling Edge to Data Remains Valid
tHSDO
4
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 4.5 V
14
VIO Above 3 V
15
VIO Above 2.7 V
16
VIO Above 2.3 V
17
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
tEN
VIO Above 4.5 V
15
VIO Above 2.7 V
18
VIO Above 2.3 V
22
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
25
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
tSSDICNV
15
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
0
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
10
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
3
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
4
SDI High to SDO High (Chain Mode with BUSY Indicator)
tDSDOSDI
VIO Above 4.5 V
15
VIO Above 2.3 V
26
1 See Figure 3 and Figure 4 for load conditions.
Unit
μs
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
500μA IOL
TO SDO
CL
50pF
1.4V
500μA IOH
Figure 3. Load Circuit for Digital Interface Timing
30% VIO
tDELAY
70% VIO
2V OR VIO – 0.5V1
0.8V OR 0.5V2
tDELAY
2V OR VIO – 0.5V1
0.8V OR 0.5V2
NOTES:
1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Rev. B | Page 5 of 24
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AD7690 arduino
1000
fS = 100kSPS
750
VDD
500
250
VIO
0
4.50 4.75 5.00 5.25
SUPPLY (V)
Figure 19. Operating Current vs. Supply
5.50
1000
750
500
250
VDD + VIO
0
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
Figure 20. Power-Down Current vs. Temperature
1000
fS = 100kSPS
750
VDD
500
250
–6
–55 –35 –15
VIO
5 25 45 65
TEMPERATURE (°C)
85 105 125
Figure 21. Operating Current vs. Temperature
AD7690
6
GAIN ERROR
4
2
0
–2
–4
–6
–55 –35 –15
ZERO ERROR
5 25 45 65
TEMPERATURE (°C)
85 105 125
Figure 22. Zero and Gain Error vs. Temperature
25
20
15
VDD = 5V, 85°C
10
VDD = 5V, 25°C
5
0
0 20 40 60 80 100 120
SDO CAPACITIVE LOAD (pF)
Figure 23. tDSDO Delay vs. Capacitance Load and Supply
Rev. B | Page 11 of 24
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