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PDF AD7687 Data sheet ( Hoja de datos )
| Número de pieza | AD7687 | |
| Descripción | Differential ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
16-Bit, 1.5 LSB INL, 250 kSPS PulSAR™
Differential ADC in MSOP/QFN
AD7687
FEATURES
16-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.4 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
Dynamic range: 96.5 dB
S/(N + D): 95.5 dB @ 20 kHz
THD: −118 dB @ 20 kHz
True differential analog input range
±VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Single-supply 2.3 V to 5.5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Daisy-chain multiple ADCs and BUSY indicator
Power dissipation
1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS, and
1.4 μW @ 2.5 V/100 SPS
Standby current: 1 nA
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin compatible with AD7685, AD7686, and AD7688
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Process controls
1.5
1.0
POSITIVE INL = +0.32LSB
NEGATIVE INL = –0.41LSB
0.5
0
–0.5
–1.0
–1.5
0
16384
32768
CODE
49152
Figure 1. Integral Nonlinearity vs. Code
65535
APPLICATION DIAGRAM
0.5V TO 5V 2.5 TO 5V
VREF
0
VREF
0
REF VDD VIO
SDI
IN+
AD7687 SCK
IN– SDO
GND
CNV
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
Figure 2.
Table 1. MSOP, QFN (LFCSP)/SOT-23 16-Bit PulSAR ADC
Type
100 kSPS 250 kSPS 500 kSPS
True Differential
AD7684
AD7687
AD7688
Pseudo
AD7683
AD7685
AD7686
Differential/Unipolar
AD7694
Unipolar
AD7680
GENERAL DESCRIPTION
The AD7687 is a 16-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single power supply, VDD, between 2.3 V to 5.5 V. It
contains a low power, high speed, 16-bit sampling ADC with no
missing codes, an internal conversion clock, and a versatile
serial interface port. The part also contains a low noise, wide
bandwidth, short aperture delay track-and-hold circuit. On the
CNV rising edge, it samples the voltage difference between IN+
and IN− pins. The voltages on these pins usually swing in
opposite phase between 0 V to REF. The reference voltage, REF,
is applied externally and can be set up to the supply voltage.
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7687 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
AD7687
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with BUSY indicator)
VIO Above 4.5 V
VIO Above 2.3 V
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min Typ Max
0.5 2.2
1.8
4
10
15
17
18
19
20
7
7
5
14
15
16
17
15
18
22
25
15
0
5
5
3
4
15
26
Unit
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. B | Page 5 of 28
Free Datasheet http://www.datasheet4u.com/
5 Page 
Data Sheet
100
95
90
SNR
S/[N + D]
ENOB
17.0
16.0
15.0
85 14.0
70 13.0
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
REFERENCE VOLTAGE (V)
Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage
100
VREF = 5V, –10dB
95
VREF = 2.5V, –10dB
90 VREF = 5V, –1dB
VREF = 2.5V, –1dB
85
80
75
70
0
100
50 100 150
FREQUENCY (kHz)
Figure 14. S/(N + D) vs. Frequency
200
VREF = 5V
95
VREF = 2.5V
90
85
80
–55 –35 –15
5 25 45 65
TEMPERATURE (°C)
85 105 125
Figure 15. SNR vs. Temperature
AD7687
–100
–105
–110
–115
–120
THD
SFDR
–125
–130
2.3
–60
2.7 3.1 3.5 3.9 4.3 4.7
REFERENCE VOLTAGE (V)
Figure 16. THD, SFDR vs. Reference Voltage
5.1
5.5
–70
–80
–90
–100
–110
VREF = 2.5V, –1dB
VREF = 5V, –1dB
VREF = 2.5V, –10dB
VREF = 5V, –10dB
–120
0
–90
50 100 150
FREQUENCY (kHz)
Figure 17. THD vs. Frequency
200
–100
–110
–120
VREF = 5V
VREF = 2.5V
–130
–55 –35 –15
5 25 45 65
TEMPERATURE (°C)
85 105 125
Figure 18. THD vs. Temperature
Rev. B | Page 11 of 28
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD7687.PDF ] | |
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