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PDF AD7686 Data sheet ( Hoja de datos )

Número de pieza AD7686
Descripción 500 kSPS PulSAR ADC
Fabricantes Analog Devices　
Logotipo Analog Devices Logotipo



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FEATURES
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR)
SINAD: 92.5 dB @ 20 kHz
THD: −110 dB @ 20 kHz
Pseudo differential analog input range
0 V to VREF with VREF up to VDD
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Daisy-chain multiple ADCs and busy indicator
Power dissipation
3.75 μW @ 5 V/100 SPS
3.75 mW @ 5 V/100 kSPS
Standby current: 1 nA
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm, 10-lead QFN (LFCSP) (SOT-23 size)
Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Process controls
2.0
POSITIVE INL = +0.52LSB
NEGATIVE INL = –0.38LSB
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
16384
32768
CODE
49152
Figure 1. Integral Nonlinearity vs. Code
65535
16-Bit, 500 kSPS PulSAR
ADC in MSOP/QFN
AD7686
FUNCTIONAL BLOCK DIAGRAM
0.5V TO 5V 5V
0 TO VREF
REF VDD VIO
IN+
SDI
AD7686 SCK
IN– SDO
GND
CNV
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
Figure 2.
Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
Type
100
kSPS
250
kSPS
400 kSPS
to
500 kSPS
18-Bit True
AD7691 AD7690
Differential
AD7982
16-Bit True
AD7684 AD7687 AD7688
Differential
AD7693
16-Bit Pseudo AD7680 AD7685 AD7686
Differential AD7683 AD7694
14-Bit Pseudo AD7940 AD7942 AD7946
Differential
1000
kSPS
AD7982
AD7980
ADC
Driver
ADA4941
ADA4841
ADA4941
ADA4841
ADA4841
ADA4841
GENERAL DESCRIPTION
The AD7686 is a 16-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5 V power supply, VDD. It contains a low power,
high speed, 16-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
the AD7686 samples an analog input IN+ between 0 V to REF
with respect to a ground sense IN−. The reference voltage, REF,
is applied externally and can be set up to the supply voltage.
Power dissipation scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus or provides an optional busy indicator. This device is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7686 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/

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AD7686 pdf
AD7686
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width ( CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min Typ Max
0.5 1.6
400
2
10
15
17
18
19
20
7
7
5
14
15
16
17
15
18
22
25
15
0
5
5
3
4
15
26
Unit
μs
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
500µA IOL
TO SDO
CL
50pF
1.4V
500µA IOH
Figure 3. Load Circuit for Digital Interface Timing
30% VIO
tDELAY
70% VIO
2V OR VIO – 0.5V1
0.8V OR 0.5V2
tDELAY
2V OR VIO – 0.5V1
0.8V OR 0.5V2
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Rev. B | Page 5 of 28
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AD7686 arduino
1000
750
VDD
fS = 100kSPS
500
250
0
4.50
4.75
VIO
5.00
SUPPLY (V)
5.25
Figure 19. Operating Currents vs. Supply
1000
5.50
750
500
250
VDD + VIO
0
–55 –35 –15
5 25 45 65
TEMPERATURE (°C)
85 105
Figure 20. Power-Down Currents vs. Temperature
125
1000
750
fS = 100kSPS
VDD = 5V
500
250
0
–55 –35 –15
VIO
5 25 45 65
TEMPERATURE (°C)
85 105
Figure 21. Operating Currents vs. Temperature
125
AD7686
4
3
2
1 OFFSET ERROR
–0
GAIN ERROR
–1
–2
–3
–4
–55 –35 –15
5 25 45 65
TEMPERATURE (°C)
85 105
Figure 22. Offset and Gain Error vs. Temperature
125
25
20
15
VDD = 5V, 85°C
10
VDD = 5V, 25°C
5
0
0 20 40 60 80 100
SDO CAPACITIVE LOAD (pF)
Figure 23. tDSDO Delay vs. Capacitance Load and Supply
120
Rev. B | Page 11 of 28
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