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PDF DP83640 Data sheet ( Hoja de datos )
| Número de pieza | DP83640 | |
| Descripción | Precision Time Protocol Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 26, 2008
DP83640
Precision PHYTER - IEEE® 1588 Precision Time Protocol
Transceiver
1.0 General Description
The DP83640 Precision PHYTER® device delivers the high-
est level of precision clock synchronization for real time in-
dustrial connectivity based on the IEEE 1588 standard. The
DP83640 has deterministic, low latency and allows choice of
microcontroller with no hardware customization required. The
integrated 1588 functionality allows system designers the
flexibility and precision of a close to the wire timestamp. The
three key 1588 features supported by the device are:
— Packet time stamps for clock synchronization
— Integrated IEEE 1588 synchronized clock generation
— Synchronized event triggering and time stamping through
GPIO
DP83640 offers innovative diagnostic features unique to Na-
tional Semiconductor, including dynamic monitoring of link
quality during standard operation for fault prediction. These
advanced features allow the system designer to implement a
fault prediction mechanism to detect and warn of deteriorating
and changing link conditions. This single port fast Ethernet
transceiver can support both copper and fiber media.
2.0 Applications
■ Factory Automation
— Ethernet/IP
— CIP Sync
■ Test and Measurement
— LXI Standard
■ Telecom
— Basestation
■ Real Time Networking
3.0 Features
■ IEEE 1588 V1 and V2 supported
■ UDP/IPv4, UDP/IPv6, and Layer2 Ethernet packets
supported
■ IEEE 1588 clock synchronization
■ Timestamp resolution of 8 ns
■ Allows sub 100 ns synchronization to master reference
■ 12 IEEE 1588 GPIOs for trigger or capture
■ Deterministic, low transmit and receive latency
■ Selectable frequency synchronized clock output
■ Dynamic Link Quality monitoring
■ TDR based Cable Diagnostic and Cable Length Detection
■ 10/100 Mb/s packet BIST (Built in Self Test)
■ Error-free Operation up to 150 meters CAT5 cable
■ ESD protection - 8 kV human body model
■ 3.3 V I/Os and MAC interface
■ Auto-MDIX for 10/100 Mbps
■ RMII Rev. 1.2 and MII MAC interface
■ 25 MHz MDC and MDIO Serial Management Interface
■ IEEE 802.3u 100BASE-FX Fiber Interface
■ IEEE 1149.1 JTAG
■ Programmable LED support for Link, 10 /100 Mb/s Mode,
Duplex, Activity, and Collision Detect
■ Optional 100BASE-TX fast link-loss detection
■ 48 pin LQFP package (7mm) x (7mm)
4.0 System Diagram
PHYTER® is a registered trademark of National Semiconductor.
© 2008 National Semiconductor Corporation 300112
30011217
www.national.com
Free Datasheet http://www.datasheet4u.com/
1 page  
14.6.9 PTP Receive Configuration Register 3 (PTP_RXCFG3), Page 5 .................................................. 95
14.6.10 PTP Receive Configuration Register 4 (PTP_RXCFG4), Page 5 ................................................ 96
14.6.11 PTP Temporary Rate Duration Low Register (PTP_TRDL), Page 5 ............................................ 96
14.6.12 PTP Temporary Rate Duration High Register (PTP_TRDH), Page 5 ........................................... 97
14.7 PTP 1588 CONFIGURATION REGISTERS - PAGE 6 .................................................................... 97
14.7.1 PTP Clock Output Control Register (PTP_COC), Page 6 ............................................................ 97
14.7.2 PHY Status Frame Configuration Register 1 (PSF_CFG1), Page 6 .............................................. 98
14.7.3 PHY Status Frame Configuration Register 2 (PSF_CFG2), Page 6 .............................................. 98
14.7.4 PHY Status Frame Configuration Register 3 (PSF_CFG3), Page 6 .............................................. 98
14.7.5 PHY Status Frame Configuration Register 4 (PSF_CFG4), Page 6 .............................................. 98
14.7.6 PTP SFD Configuration Register (PTP_SFDCFG), Page 6 ......................................................... 99
14.7.7 PTP Interrupt Control Register (PTP_INTCTL), Page 6 .............................................................. 99
14.7.8 PTP Clock Source Register (PTP_CLKSRC), Page 6 ................................................................. 99
14.7.9 PTP Ethernet Type Register (PTP_ETR), Page 6 ...................................................................... 99
14.7.10 PTP Offset Register (PTP_OFF), Page 6 .............................................................................. 100
14.7.11 PTP GPIO Monitor Register (PTP_GPIOMON), Page 6 .......................................................... 100
14.7.12 PTP Receive Hash Register (PTP_RXHASH), Page 6 ............................................................ 100
15.0 Absolute Maximum Ratings ......................................................................................................... 101
16.0 AC and DC Specifications ........................................................................................................... 101
16.1 DC SPECIFICATIONS ............................................................................................................. 101
16.2 AC SPECIFICATIONS .............................................................................................................. 102
16.2.1 Power Up Timing ................................................................................................................ 102
16.2.2 Reset Timing ...................................................................................................................... 103
16.2.3 MII Serial Management Timing ............................................................................................. 104
16.2.4 100 Mb/s MII Transmit Timing ............................................................................................... 104
16.2.5 100 Mb/s MII Receive Timing ................................................................................................ 105
16.2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing ......................................... 105
16.2.7 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion Timing ................................... 106
16.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) ............................................................................ 106
16.2.9 100BASE-TX and 100BASE-FX MII Receive Packet Latency Timing ......................................... 107
16.2.10 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion Timing ................................. 107
16.2.11 10 Mb/s MII Transmit Timing ............................................................................................... 108
16.2.12 10 Mb/s MII Receive Timing ................................................................................................ 108
16.2.13 10BASE-T MII Transmit Timing (Start of Packet) ................................................................... 109
16.2.14 10BASE-T MII Transmit Timing (End of Packet) .................................................................... 109
16.2.15 10BASE-T MII Receive Timing (Start of Packet) .................................................................... 110
16.2.16 10BASE-T MII Receive Timing (End of Packet) ..................................................................... 110
16.2.17 10 Mb/s Heartbeat Timing .................................................................................................. 111
16.2.18 10 Mb/s Jabber Timing ...................................................................................................... 111
16.2.19 10BASE-T Normal Link Pulse Timing ................................................................................... 112
16.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing ...................................................................... 112
16.2.21 100BASE-TX Signal Detect Timing ..................................................................................... 113
16.2.22 100 Mb/s Internal Loopback Timing ..................................................................................... 113
16.2.23 10 Mb/s Internal Loopback Timing ...................................................................................... 114
16.2.24 RMII Transmit Timing (Slave Mode) ..................................................................................... 114
16.2.25 RMII Transmit Timing (Master Mode) ................................................................................... 115
16.2.26 RMII Receive Timing (Slave Mode) ...................................................................................... 116
16.2.27 RMII Receive Timing (Master Mode) .................................................................................... 117
16.2.28 RX_CLK Timing (RMII Master Mode) ................................................................................... 118
16.2.29 CLK_OUT Timing (RMII Slave Mode) ................................................................................... 118
16.2.30 Single Clock MII (SCMII) Transmit Timing ............................................................................ 119
16.2.31 Single Clock MII (SCMII) Receive Timing .............................................................................. 120
16.2.32 100 Mb/s X1 to TX_CLK Timing .......................................................................................... 121
17.0 Physical Dimensions .................................................................................................................. 122
5 www.national.com
5 Page 
Signal Name
RX_ER
Pin Name
RX_ER
RXD_0
RXD_1
RXD_2
RXD_3
RXD_0
RXD_1
RXD_2
RXD_3
CRS/CRS_DV CRS/CRS_DV
COL
COL
Type
S, O, PD
S, O, PD
S, O, PU
S, O, PU
Pin #
Description
41 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to
indicate that an invalid symbol has been detected within a received packet
in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever a
media error is detected, and RX_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in RMII mode, since the PHY
is required to corrupt data on a receive error.
46 MII RECEIVE DATA: Nibble wide receive data signals driven
45 synchronously to the RX_CLK (25 MHz for 100 Mb/s mode, 2.5 MHz for
44 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is
43 asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven
synchronously to the 50 MHz reference clock.
40 MII CARRIER SENSE: Asserted high to indicate the receive medium is
non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines
the RMII Carrier and Receive Data Valid indications. For a detailed
description of this signal, see the RMII Specification.
42 MII COLLISION DETECT: Asserted high to indicate detection of a
collision condition (simultaneous transmit and receive activity) in 10 Mb/
s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is
also asserted for a duration of approximately 1µs at the end of
transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is
always logic 0. There is no heartbeat function during 10 Mb/s full duplex
operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is
required. The MAC will recover CRS from the CRS_DV signal and use
that along with its TX_EN signal to determine collision.
11 www.national.com
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| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet DP83640.PDF ] | |
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