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AD7960 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7960
Beschreibung 5 MSPS PulSAR Differential ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD7960 Datasheet, Funktion
Data Sheet
FEATURES
Throughput: 5 MSPS
18-bit resolution with no missing codes
Excellent ac and dc performance
Dynamic range: 100 dB
SNR: 99 dB
THD: −117 dB
INL: ±0.8 LSB (typical), ±2 LSB (maximum)
DNL: ±0.5 LSB (typical), ±0.99 LSB (maximum)
True differential analog input voltage range: ±4.096 V or ±5 V
Low power dissipation
46.5 mW at 5 MSPS with external reference buffer
(echoed clock mode)
64.5 mW at 5 MSPS with internal reference buffer
(echoed clock mode)
39 mW at 5 MSPS with external reference buffer
(self clocked mode, CNV± in CMOS mode)
SAR architecture
No latency/pipeline delay
External reference options: 2.048 V buffered to 4.096 V (internal
reference buffer), 4.096 V, and 5 V
Serial LVDS interface
Self clocked mode
Echoed clock mode
LVDS or CMOS option for conversion control (CNV± signal)
Operating temperature range of −40°C to +85°C
32-lead, 5mm × 5mm LFCSP (QFN)
APPLICATIONS
Digital imaging systems
Digital X-rays
Computed tomography
IR cameras
MRI gradient control
High speed data acquisition
Spectroscopy
Test equipment
18-Bit, 5 MSPS PulSAR
Differential ADC
AD7960
FUNCTIONAL BLOCK DIAGRAM
REFIN REF VCM VDD1 VDD2 VIO
IN+
IN–
AD7960
÷2 CLOCK
CAP
DAC
LOGIC
SAR
SERIAL
LVDS
EN0
EN1
EN2
EN3
CNV+, CNV–
D+, D–
DCO+, DCO–
CLK+, CLK–
GND
Figure 1.
GENERAL DESCRIPTION
The AD7960 is an 18-bit, 5 MSPS, charge redistribution successive
approximation (SAR), analog-to-digital converter (ADC). The
SAR architecture allows unmatched performance both in noise
and in linearity. The AD7960 contains a low power, high speed,
18-bit sampling ADC, an internal conversion clock, and an
internal reference buffer. On the CNV± edge, the AD7960
samples the voltage difference between the IN+ and IN− pins.
The voltages on these pins swing in opposite phase between 0 V
and 4.096 V and between 0 V and 5 V. The reference voltage is
applied to the part externally. All conversion results are available
on a single LVDS self clocked or echoed clock serial interface.
The AD7960 is available in a 32-lead LFCSP (QFN) with
operation specified from −40°C to +85°C.
Table 1. Fast PulSAR® ADC Selection
Input Type
1 MSPS to 2 MSPS to
<2 MSPS 3 MSPS
Differential,1 AD7653
AD7985
16-Bit
AD7667
AD7980
AD7983
True Bipolar, AD7671
16-Bit
Differential,2
16-Bit
AD7677
AD7623
AD7621
AD7622
Differential,2 AD7643
AD7641
18-Bit
AD7982
AD7986
AD7984
5 MSPS
to 6 MSPS 10 MSPS
AD7625
AD7961
AD7960
AD7626
1 Ground sense.
2 Antiphase.
Rev. 0
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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AD7960 Datasheet, Funktion
AD7960
Data Sheet
Timing Diagrams
CNV–
CNV+
SAMPLE N
tCNVH
tCYC
SAMPLE N + 1
tACQ
ACQUISITION
tCLK
CLK–
CLK+
DCO–
tDCO
DCO+
D+
tCLKD
D–
17 18
ACQUISITION
12
tCLKL
17 18
ACQUISITION
123
17 18
12
17 18
tMSB
tD
D1 D0
N–1 N–1
0
D17 D16
NN
D1 D0
NN
Figure 2. Echoed Clock Interface Mode Timing Diagram
0
123
D17
N+1
D16 D15
N+1 N+1
SAMPLE N
tCNVH
tCYC
SAMPLE N + 1
CNV–
CNV+
tACQ
ACQUISITION
CLK–
CLK+
tCLKD
D+
D–
tCLK
19 20
ACQUISITION
tCLKL
1234
19 20
ACQUISITION
123
tMSB
D1
N–1
D0
N–1
0
1
0
D17 D16
NN
D1
N
Figure 3. Self Clocked Interface Mode Timing Diagram
D0
N
0
1
0
D17
N+1
Rev. 0 | Page 6 of 24

6 Page









AD7960 pdf, datenblatt
AD7960
2.5
2.0
GAIN ERROR
1.5
1.0
ZERO ERROR
0.5
0
–40 –20
0
20 40 60 80 100
TEMPERATURE (°C)
Figure 23. Zero Error and Gain Error vs. Temperature, REF = 5 V
0.3
0.2
0.1
0 IN+
–0.1
–0.2
IN–
–0.3
–0.4
–0.5
–0.6
–0.7
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIFFERENTIAL INPUT VOLTAGE (V)
Figure 24. Input Current (IN+, IN−) vs. Differential Input Voltage, REF = 5 V
14
12
VDD2
10
8
6
VIO
4
VDD1
2
0
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
Figure 25. Supply Current vs. Temperature, REF = 5 V, Self Clocked Mode,
CNV± in CMOS Mode, Internal Reference Buffer Disabled
Data Sheet
10
VDD2
VDD1
VIO
8
6
4
2
0
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
Figure 26. Power-Down Current vs. Temperature, REF = 5 V
12
10
VDD2
8
6
VIO
4
2
VDD1
0
012345
THROUGHPUT (MHz)
Figure 27. Supply Current vs. Throughput, Self Clocked Mode, CNV± in CMOS
Mode, Internal Reference Buffer Disabled
Rev. 0 | Page 12 of 24

12 Page





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