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ADXL375 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADXL375
Beschreibung Digital Accelerometer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADXL375 Datasheet, Funktion
Data Sheet
FEATURES
Low power: as low as 35 µA in measurement mode and
0.1 µA in standby mode at VS = 2.5 V
Power consumption scales automatically with bandwidth
Embedded, 32-level FIFO buffer minimizes processor load
Bandwidth of up to 1 kHz
Bandwidth selectable via serial command
Shock event detection
Activity/inactivity monitoring
Supply voltage range: 2.0 V to 3.6 V
I/O voltage range: 1.7 V to VS
SPI (3- or 4-wire) and I2C digital interfaces
Wide temperature range: −40°C to +85°C
10,000 g shock survival
Pb free/RoHS compliant
Small and thin: 3 mm × 5 mm × 1 mm LGA package
APPLICATIONS
Concussion and head trauma detection
High force event detection
3-Axis, ±200 g
Digital Accelerometer
ADXL375
GENERAL DESCRIPTION
The ADXL375 is a small, thin, 3-axis accelerometer that provides
low power consumption and high resolution measurement up
to ±200 g. The digital output data is formatted as 16-bit, twos
complement data and is accessible through a SPI (3- or 4-wire)
or I2C digital interface.
An integrated memory management system with a 32-level first in,
first out (FIFO) buffer can be used to store data to minimize host
processor activity and lower overall system power consumption.
Low power modes enable intelligent motion-based power
management with threshold sensing and active acceleration
measurement at extremely low power dissipation.
The ADXL375 is supplied in a small, thin, 3 mm × 5 mm ×
1 mm, 14-lead LGA.
ADXL375
FUNCTIONAL BLOCK DIAGRAM
VS VDD I/O
POWER
MANAGEMENT
3-AXIS
SENSOR
SENSE
ELECTRONICS
ADC
DIGITAL
FILTER
CONTROL
AND
INTERRUPT
LOGIC
INT1
INT2
GND
32-LEVEL
FIFO
Figure 1.
SERIAL I/O
CS
SDA/SDI/SDIO
SDO/ALT
ADDRESS
SCL/SCLK
Rev. 0
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ADXL375 Datasheet, Funktion
ADXL375
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADXL375
TOP VIEW
(Not to Scale)
SCL/SCLK
VDD I/O 1 14 13 SDA/SDI/SDIO
GND 2
12 SDO/ALT ADDRESS
RESERVED
GND
GND
3 11
+X
4 +Y
10
+Z
59
RESERVED
NC
INT2
VS 6 7 8 INT1
CS
NOTES
1. NC = NOT INTERNALLY CONNECTED.
Figure 3. Pin Configuration
Data Sheet
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 VDD I/O
2 GND
Digital Interface Supply Voltage.
Ground. This pin must be connected to ground.
3
RESERVED
Reserved. This pin must be connected to VS or left open.
4 GND
Ground. This pin must be connected to ground.
5 GND
Ground. This pin must be connected to ground.
6 VS
7 CS
Supply Voltage.
Chip Select.
8 INT1
Interrupt 1 Output.
9 INT2
Interrupt 2 Output.
10 NC
Not Internally Connected.
11
RESERVED
Reserved. This pin must be connected to ground or left open.
12 SDO/ALT ADDRESS SPI 4-Wire Serial Data Output (SDO)/I2C Alternate Address Select (ALT ADDRESS).
13
SDA/SDI/SDIO
I2C Serial Data (SDA)/SPI 4-Wire Serial Data Input (SDI)/SPI 3-Wire Serial Data Input and Output (SDIO).
14 SCL/SCLK I2C Serial Communications Clock (SCL)/SPI Serial Communications Clock (SCLK).
Rev. 0 | Page 6 of 32

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ADXL375 pdf, datenblatt
ADXL375
Trigger Mode
In trigger mode, the FIFO buffer accumulates samples, storing
the latest 32 samples from measurements of the x-, y-, and z-axes.
After a trigger event occurs, an interrupt is sent to the INT1 or
INT2 pin (determined by the trigger bit in the FIFO_CTL register),
and the FIFO_TRIG bit (Bit D7) is set in the FIFO_STATUS
register (Address 0x39).
The FIFO buffer keeps the last n samples (n is the value specified
by the samples bits in the FIFO_CTL register) and then operates
in FIFO mode, collecting new samples only when the FIFO buffer
is not full. A delay of at least 5 µs must elapse between the occur-
rence of the trigger event and the start of data readback from the
FIFO buffer to allow the buffer to discard and retain the necessary
samples.
Additional trigger events cannot be recognized until the part is
reset to trigger mode. To reset the part to trigger mode,
1. If desired, read data from the FIFO buffer (see the Retrieving
Data from the FIFO Buffer section).
Before resetting the part to trigger mode, read back the
FIFO data; placing the device into bypass mode clears the
FIFO buffer.
2. Configure the device for bypass mode by setting Bits[D7:D6]
at Address 0x38 to 00.
3. Configure the device for trigger mode by setting Bits[D7:D6]
at Address 0x38 to 11.
Retrieving Data from the FIFO Buffer
When the FIFO buffer operates in FIFO, stream, or trigger mode,
FIFO data can be read from the data registers (Address 0x32 to
Address 0x37). Each time data is read from the FIFO buffer, the
oldest x-, y-, and z-axis data is moved into the DATAX, DATAY,
and DATAZ registers.
If a single-byte read operation is performed, the remaining bytes
of data for the current FIFO sample are lost. Therefore, data for
all axes of interest must be read in a burst (multiple-byte) read
operation. To ensure that the FIFO buffer is empty (that is, all
new data has moved into the data registers), an interval of at
least 5 µs must elapse between the end of the readback from the
data registers and the start of a new read of the data registers or
the FIFO_STATUS register (Address 0x39). The end of a read
operation from the data registers is signified by the transition
from Register 0x37 to Register 0x38 or by the CS pin going high.
Data Sheet
When SPI operation is enabled at a frequency of 1.6 MHz or
lower, the register addressing portion of the transmission provides
a sufficient delay to ensure that the FIFO buffer has completely
emptied. When SPI operation is enabled at a frequency higher
than 1.6 MHz, the CS pin must be deasserted to ensure a total
delay of 5 µs; otherwise, the delay is not sufficient. When SPI
operation is enabled at 5 MHz, the total delay necessary is at
most 3.4 µs.
When I2C mode is enabled on the part, the communication rate
is low enough to ensure a sufficient delay between FIFO reads.
SELF-TEST
The ADXL375 incorporates a self-test feature that effectively
tests its mechanical and electronic systems simultaneously. When
the self-test function is enabled (via the SELF_TEST bit in the
DATA_FORMAT register, Address 0x31), an electrostatic force
is exerted on the mechanical sensor.
This electrostatic force moves the mechanical sensing element in
the same manner as acceleration, and it is additive to the external
acceleration experienced by the device. This added electrostatic
force results in an output change in the x-, y-, and z-axes. Because
the electrostatic force is proportional to VS2, the output change
varies with VS.
The self-test response in the x- and y-axes exhibits bimodal
behavior and, therefore, is not always a reliable indicator of
sensor health or potential shift in device sensitivity. For this
reason, perform the self-test check in the z-axis.
Use of the self-test feature at data rates of less than 100 Hz or at
1600 Hz may yield values outside the limits shown in Figure 16.
For the self-test function to operate correctly, the part must be in
normal power operation (LOW_POWER bit = 0 in the BW_RATE
register, Address 0x2C) and be configured for a data rate from
100 Hz to 800 Hz, or for a data rate of 3200 Hz (see Table 6).
For more information about the self-test feature, see the Using
Self-Test section.
Rev. 0 | Page 12 of 32

12 Page





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