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ADP5061 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP5061
Beschreibung Tiny I2C Programmable Linear Battery Charger
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADP5061 Datasheet, Funktion
Data Sheet
Tiny I2C Programmable Linear Battery Charger
with Power Path and USB Mode Compatibility
ADP5061
FEATURES
2.6 mm × 2 mm WLCSP package
Fully programmable via I2C
Flexible digital control inputs
Up to 2.1 A current from an ac charger in LDO mode
Operating input voltage from 4.0 V to 6.7 V
Tolerant input voltage from −0.5 V to +20 V (USB VBUS)
Fully compatible with USB 3.0 and USB Battery Charging
Specification 1.2
Built-in current sensing and limiting
As low as 30 mΩ battery isolation FET between battery and
charger output
Thermal regulation prevents over heating
Compliant with JEITA 1 and JEITA 2 Li-Ion battery charging
temperature specifications
SYS_EN flag permits the system to be disabled until battery is at
minimum required level for guaranteed system start-up
APPLICATIONS
Digital still cameras
Digital video cameras
Single cell Li-Ion portable equipment
PDAs, audio, and GPS devices
Portable medical devices
Mobile phones
GENERAL DESCRIPTION
The ADP5061 charger is fully compliant with USB 3.0 and the
USB Battery Charging Specification 1.2 and enables charging
via the mini USB VBUS pin from a wall charger, car charger, or
USB host port.
The ADP5061 operates from a 4 V to 6.7 V input voltage range
but is tolerant of voltages up to 20 V. The 20 V voltage tolerance
alleviates the concerns about the USB bus spiking during dis-
connect or connect scenarios.
The ADP5061 features an internal FET between the linear
charger output and the battery. This permits battery isolation
and, hence, system powering under a dead battery or no battery
TYPICAL APPLICATION CIRCUIT
AC OR
USB
VBUS
C1
10µF
VIN
CBP
C2
10nF
ADP5061
ISO_S
SYSTEM
C3
47µF
SCL
SDA
DIG_IO1
DIG_IO2
DIG_IO3
SYS_EN
CHARGER
CONTROL
BLOCK
AGND
Figure 1.
ISO_B
BAT_SNS
+ Li-ion
THR
C4
22µF
ILED
VLED
http://www.DataSheet4U.com/
scenario, which allows for immediate system function on connec-
tion to a USB power supply.
Based on the type of USB source, which is detected by an external
USB detection chip, the ADP5061 can be set to apply the correct
current limit for optimal charging and USB compliance.
The ADP5061 has three factory programmable digital input/output
pins that provide maximum flexibility for different systems.
These digital input/output pins permit combinations of features
such as, input current limits, charging enable and disable,
charging current limits, and a dedicated interrupt output pin.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.






ADP5061 Datasheet, Funktion
ADP5061
Data Sheet
RECOMMENDED INPUT AND OUTPUT CAPACITANCES
Table 2.
Parameter
CAPACITANCES
VINx
CBP
ISO_Sx
ISO_Bx
Symbol
CVIN
CBP
CISO_S
CISO_B
Min Typ Max Unit Test Conditions/Comments
4 10 μF
6
10 14
nF
20 47 100 μF
10 22
μF
Effective capacitance
Effective capacitance
Effective capacitance
Effective capacitance
I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Table 3.
Parameter1
I2C-COMPATIBLE INTERFACE2
Capacitive Load for Each Bus Line
SCL Clock Frequency
SCL High Time
SCL Low Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Hold Time for Start/Repeated Start
Bus Free Time Between a Stop and a Start Condition
Setup Time for Stop Condition
Rise Time of SCL/SDA
Fall Time of SCL/SDA
Pulse Width of Suppressed Spike
Symbol Min Typ Max Unit Test Conditions/Comments
CS
fSCL
tHIGH
tLOW
tSU, DAT
tHD, DAT
tSU, STA
tHD, STA
tBUF
tSU, STO
tR
tF
tSP
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20
20
http://www.DataSheet4U.com/
0
400 pF
400 kHz
µs
µs
ns
0.9 µs
µs
µs
µs
µs
300 ns
300 ns
50 ns
1 Guaranteed by design.
2 A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2).
Timing Diagram
SDA
SCL
tLOW
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
tR tSU, DAT
tF
tF
tHD, STA
tHD, DAT
tHIGH
tBU, STA
Sr
Figure 2. I2C Timing Diagram
tSP tR
tBUF
tBU, STO
PS
Rev. 0 | Page 6 of 44

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ADP5061 pdf, datenblatt
ADP5061
1.4
1.3 ICHG = 1300mA
1.2
1.1
1.0
0.9
0.8
ICHG = 750mA
0.7
0.6
ICHG = 500mA
0.5
0.4
–40 –15
10
35
60
85 110
AMBIENT TEMPERATURE (°C)
Figure 20. Fast Charge CC Mode Current vs. Ambient Temperature
7.00
6.95
6.90
6.85
6.80
–40 –25 –10 5 20 35 50 65 80 95 110 125
AMBIENT TEMPERATURE (°C)
Figure 21. VINx Overvoltage Threshold vs. Ambient Temperature
Data Sheet
1.6
1.5
1.4 ILIM = 1500mA
1.3
1.2
1.1
1.0
0.9 ILIM = 900mA
0.8
0.7
0.6
0.5 ILIM = 500mA
0.4
0.3
0.2
0.1
ILIM = 100mA
0
–40 –25 –10 5
20 35 50 65 80 95 110 125
AMBIENT TEMPERATURE (°C)
Figure 22. Input Current Limit vs. Ambient Temperature
http://www.DataSheet4U.com/
Rev. 0 | Page 12 of 44

12 Page





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