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ADP5050 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP5050
Beschreibung 5-Channel Integrated Power Solution
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADP5050 Datasheet, Funktion
Data Sheet
5-Channel Integrated Power Solution with Quad
Buck Regulators and 200 mA LDO Regulator
ADP5050
FEATURES
Wide input voltage range: 4.5 V to 15 V
±1.5% output accuracy over full temperature range
250 kHz to 1.4 MHz adjustable switching frequency
Adjustable/fixed output options via factory fuse or I2C interface
I2C interface with interrupt on fault conditions
Power regulation
Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A
sync buck regulators with low-side FET driver
Channel 3 and Channel 4: 1.2 A sync buck regulators
Channel 5: 200 mA low dropout (LDO) regulator
Single 8 A output (Channel 1 and Channel 2 operated in parallel)
Dynamic voltage scaling (DVS) for Channel 1 and Channel 4
Precision enable with 0.8 V accurate threshold
Active output discharge switch
Programmable phase shift in 90° steps
Individual channel FPWM/PSM mode selection
Frequency synchronization input or output
Optional latch-off protection on OVP/OCP failure
Power-good flag on selected channels
Low input voltage detection
Overheat detection on junction temperature
UVLO, OCP, and TSD protection
48-lead, 7 mm × 7 mm LFCSP package
−40°C to +125°C junction temperature
APPLICATIONS
Small cell base stations
FPGA and processor applications
Security and surveillance
Medical applications
GENERAL DESCRIPTION
The ADP5050 combines four high performance buck regulators
and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP
package that meets demanding performance and board space
requirements. The device enables direct connection to high input
voltages up to 15 V with no preregulators.
Channel 1 and Channel 2 integrate high-side power MOSFETs and
low-side MOSFET drivers. External NFETs can be used in low-side
power devices to achieve an efficiency optimized solution and
deliver a programmable output current of 1.2 A, 2.5 A, or 4 A.
Combining Channel 1 and Channel 2 in a parallel configuration
can provide a single output with up to 8 A of current.
Channel 3 and Channel 4 integrate both high-side and low-side
MOSFETs to deliver output current of 1.2 A.
TYPICAL APPLICATION CIRCUIT
C1
4.5V TO 15V
VREG
VDD
C0
PVIN1
C2
COMP1
EN1
SS12
ADP5050
INT VREG
100mA
OSCILLATOR
CHANNEL 1
BUCK REGULATOR
(1.2A/2.5A/4A)
VREG
SYNC/MODE
RT
FB1
BST1
SW1
C3
DL1 Q1
PGND RILIM1
DL2 RILIM2
PVIN2
C5
COMP2
EN2
CHANNEL 2
BUCK REGULATOR
(1.2A/2.5A/4A)
VREG
SW2
Q2
BST2
FB2
C6
L1
L2
VOUT1
C4
VOUT2
C7
PVIN3
C8
COMP3
EN3
SS34
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PVIN4
C11
COMP4
EN4
1.7V TO 5.5V PVIN5
C14 EN5
VDDIO
SCL
SDA
CHANNEL 3
BUCK REGULATOR
(1.2A)
CHANNEL 4
BUCK REGULATOR
(1.2A)
CHANNEL 5
200mA LDO
REGULATOR
I2C ALERT
BST3
SW3
C9
FB3
PGND3
BST4
SW4
FB4
C12
PGND4
VOUT5
FB5
PWRGD
nINT
L3 VOUT3
C10
L4 VOUT4
C13
VOUT5
C15
EXPOSED PAD
Figure 1.
The switching frequency of the ADP5050 can be programmed
or synchronized to an external clock. The ADP5050 contains a
precision enable pin on each channel for easy power-up sequencing
or adjustable UVLO threshold.
The ADP5050 integrates a general-purpose LDO regulator with
low quiescent current and low dropout voltage that provides up
to 200 mA of output current.
The optional I2C interface provides the user with flexible
configuration options, including adjustable and fixed output
voltage options, junction temperature overheat warning, low
input voltage detection, and dynamic voltage scaling (DVS).
Rev. 0
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADP5050 Datasheet, Funktion
ADP5050
Data Sheet
Parameter
LOW INPUT VOLTAGE DETECTION
Low Input Voltage Threshold
Symbol
VLVIN-TH
Low Input Voltage Threshold Range
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
THERMAL OVERHEAT WARNING
Thermal Overheat Threshold
Overheat Threshold Range
Thermal Overheat Hysteresis
TSHDN
THYS
THOT
THOT(HYS)
Min
4.07
10.05
4.2
105
Typ
4.236
10.25
150
15
115
5
Max
4.39
10.4
11.2
125
Unit Test Conditions/Comments
V LVIN_TH[3:0] = 0000
V LVIN_TH[3:0] = 1100
V I2C programmable (4-bit value)
°C
°C
°C TEMP_TH[1:0] = 10
°C I2C programmable (2-bit value)
°C
BUCK REGULATOR SPECIFICATIONS
VIN = 12 V, VVREG = 5.1 V, fSW = 600 kHz for all channels, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C
for typical specifications, unless otherwise noted.
Table 2.
Parameter
CHANNEL 1 SYNC BUCK REGULATOR
FB1 Pin
Fixed Output Options
Adjustable Feedback Voltage
Feedback Voltage Accuracy
Symbol
VOUT1
VFB1
VFB1(DEFAULT)
Feedback Bias Current
SW1 Pin
High-Side Power FET
On Resistance
Current-Limit Threshold
IFB1
RDSON(1H)
ITH(ILIM1)
Minimum On Time
Minimum Off Time
Low-Side Driver, DL1 Pin
Rising Time
Falling Time
Sourcing Resistor
Sinking Resistor
Error Amplifier (EA), COMP1 Pin
EA Transconductance
Soft Start
Soft Start Time
Programmable Soft Start Range
Hiccup Time
COUT Discharge Switch On Resistance
tMIN_ON1
tMIN_OFF1
tRISING1
tFALLING1
tSOURCING1
tSINKING1
gm1
tSS1
tHICCUP1
RDIS1
Min
0.85
−0.55
−1.25
−1.5
3.50
1.91
4.95
310
2.0
Typ Max
0.800
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1.60
+0.55
+1.0
+1.5
0.1
100
4.4
2.63
6.44
117
1/9 × tSW
5.28
3.08
7.48
155
20
3.4
10
0.95
470 620
2.0
7 × tSS1
250
8.0
Unit Test Conditions/Comments
V Fuse trim or I2C interface
(5-bit value)
V
% TJ = 25°C
% 0°C ≤ TJ ≤ 85°C
% −40°C ≤ TJ ≤ +125°C
µA Adjustable voltage
mΩ Pin-to-pin measurement
A RILIM1 = floating
A RILIM1 = 47 kΩ
A RILIM1 = 22 kΩ
ns fSW = 250 kHz to 1.4 MHz
ns fSW = 250 kHz to 1.4 MHz
ns CISS = 1.2 nF
ns CISS = 1.2 nF
µS
ms SS12 connected to VREG
ms
ms
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ADP5050 pdf, datenblatt
ADP5050
Data Sheet
Pin No.
30
31
32
33, 34
35, 36
37
38
39
40
41
42
43
44
45
46
47
48
Mnemonic
PGND
DL1
BST1
SW1
PVIN1
EN1
SS12
COMP1
FB1
RT
VDD
SYNC/MODE
VREG
FB3
COMP3
SS34
EN3
EPAD
Description
Power Ground for Channel 1 and Channel 2.
Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current-limit
threshold for Channel 1.
High-Side FET Driver Power Supply for Channel 1.
Switching Node Output for Channel 1.
Power Input for the Internal 5.1 V VREG Linear Regulator and the Channel 1 Buck Regulator. Connect a bypass
capacitor between this pin and ground.
Enable Input for Channel 1. An external resistor divider can be used to set the turn-on threshold.
Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 1 and
Channel 2 (see the Soft Start section). This pin is also used to configure parallel operation of Channel 1 and
Channel 2 (see the Parallel Operation section).
Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground.
Feedback Sensing Input for Channel 1.
Connect a resistor from RT to ground to program the switching frequency from 250 kHz to 1.4 MHz. For more
information, see the Oscillator section.
Output of the Internal 3.3 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground.
Synchronization Input/Output (SYNC). To synchronize the switching frequency of the part to an external clock,
connect this pin to an external clock with a frequency from 250 kHz to 1.4 MHz. This pin can also be configured
as a synchronization output using the I2C interface or by factory fuse.
Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, each channel operates
in forced PWM or automatic PWM/PSM mode, as specified by the PSMx_ON bits in Register 6. When this pin is
logic low, all channels operate in automatic PWM/PSM mode, and the PSMx_ON settings in Register 6 are ignored.
Output of the Internal 5.1 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground.
Feedback Sensing Input for Channel 3.
Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground.
Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 3 and
Channel 4 (see the Soft Start section).
Enable Input for Channel 3. An external resistor divider can be used to set the turn-on threshold.
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Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane.
Rev. 0 | Page 12 of 60

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