PDF ADRF6518 Data sheet ( Hoja de datos )

Número de pieza	ADRF6518
Descripción	Dual Programmable Filters and Variable Gain Amplifiers
Fabricantes	Analog Devices
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Preliminary Technical Data 63 MHz Dual Programmable Filters and Variable Gain Amplifiers ADRF6518 FEATURES Matched pair of programmable filters and triple VGAs Continuous gain control range: 72 dB Digital gain control: 30 dB 6-pole Butterworth filter: 1 MHz to 63 MHz in 1 MHz steps, 1 dB corner frequency Preamplifier and postamplifier gain steps Peak detector Filter bypass mode, −3 dB bandwidth (BW) VGA2 and VGA3 21 dB/12 dB gain: 350 MHz/700 MHz IMD3: >65 dBc for 1.5 V p-p composite output HD2, HD3: >65 dBc for 1.5 V p-p output Differential input and output Flexible output and input common-mode ranges Optional dc output offset correction SPI programmable filter corners and gain steps Single 3.3 V supply operation with power-down feature APPLICATIONS Baseband I/Q receivers Diversity receivers ADC drivers Point-to-point and point-to-multipoint radios Instrumentation Medical GENERAL DESCRIPTION The ADRF6518 is a matched pair of fully differential low noise and low distortion programmable filters and variable gain amplifiers (VGAs). Each channel is capable of rejecting large out-of-band interferers while reliably boosting the wanted signal, thus reducing the bandwidth and resolution requirements on the analog-to- digital converters (ADCs). The excellent matching between channels and their high spurious-free dynamic range over all gain and bandwidth settings make the ADRF6518 ideal for quadrature-based (IQ) communication systems with dense constellations, multiple carriers, and nearby interferers. The various amplifier gains, filter corners and other features are all programmable via a serial port interface (SPI) port. The first VGA that precedes the filters offers 24 dB of continuous gain control with fixed gain options of 9 dB, 12 dB, and 15 dB, and sets a differential input impedance of 400 Ω. The filters provide a six-pole Butterworth response with 1 dB corner frequencies from 1 MHz to 63 MHz in 1 MHz steps. For operation beyond 63 MHz, the filter can be disabled and completely bypassed via the SPI. A wideband peak detector is available to monitor the FUNCTIONAL BLOCK DIAGRAM http://www.DataSheet4U.net/ Figure 1. peak signal at the filter inputs. The pair of VGAs that follow the filters each provides 24 dB of continuous gain control with fixed gain options of 12 dB, 15 dB, 18 dB, and 21 dB. The output buffers offer an additional option of 3 dB or 9 dB gain and provide a differential output impedance of less than 10 Ω. They are capable of driving 3 V p-p into 1 kΩ loads at better than 65 dBc HD3. The output common-mode voltage defaults to VPS/2 and can be adjusted down to 900 mV by driving the high impedance VOCM pin. Independent, built-in dc offset correction loops for each channel can be disabled via the SPI if fully dc-coupled operation is desired. The high-pass corner frequency is deter- mined by external capacitors on the OFS1 and OFS2 pins and the postfilter VGA gain. The ADRF6518 operates from a 3.15 V to 3.45 V supply and consumes a maximum supply current of 400 mA. When fully disabled, it consumes <10 mA. The ADRF6518 is fabricated in an advanced silicon-germanium BiCMOS process and is available in a 32-lead, exposed pad LFCSP. Performance is specified over the −40°C to +85°C temperature range. Rev. PrA Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com datasheet pdf - http://www.DataSheet4U.net/ 1 page Preliminary Technical Data ADRF6518 TIMING DIAGRAMS tCLK tPW CLK tLS tLH LE tDS tDH DATA WRITE BIT LSB B2 B3 B4 B5 B6 B7 MMSBSB - 2 NOTES 1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 8-BIT WORD IS THEN WRITTEN TO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK. Figure 2. Write Mode Timing Diagram CLK LE DATA tD tLS tCLK tPW tLH tDS tDH READ BIT DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’DTOCNA'TRECARDEON’T CARE SDO LSB B2 B3 B4 B5 B6 B7 MSB NOTES 1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE 8-BIT WORD IS THEN REGISTERED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES OF THE CLOCK. Figure 3. Read Mode Timing Diagram http://www.DataSheet4U.net/ Rev. PrA \| Page 5 of 36 datasheet pdf - http://www.DataSheet4U.net/ 5 Page Preliminary Technical Data ADRF6518 Figure 23. Noise Figure vs. Analog Gain over BW setting; Digital Gain = 0000001 Figure 26. Output Noise Density vs. Frequency; BW = 7 MHz, Digital Gain = 0000001 http://www.DataSheet4U.net/ Figure 24. Output Noise Density vs. Analog Gain over Digital Gain; BW = 63 MHz Figure 27. Output Noise Density vs. Frequency; BW = 60 MHz, Digital Gain = 0000001 Figure 25. Output Noise Density vs. Gain over Bandwidth Setting; Digital Gain = 0000001 Figure 28. Output Noise Density vs. Input CW Block level; BW = 63 MHz, Digital Gain = 0000001 Rev. PrA \| Page 11 of 36 datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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