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PDF ADRF6516 Data sheet ( Hoja de datos )
| Número de pieza | ADRF6516 | |
| Descripción | Dual Programmable Filters | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
31 MHz, Dual Programmable Filters
and Variable Gain Amplifiers
ADRF6516
FEATURES
Matched pair of programmable filters and VGAs
Continuous gain control range: 50 dB
Digital gain control: 15 dB
6-pole Butterworth filter: 1 MHz to 31 MHz
in 1 MHz steps, 1 dB corner frequency
Preamplifier and postamplifier gain steps
IMD3: >65 dBc for 1.5 V p-p composite output
HD2, HD3: >65 dBc for 1.5 V p-p output
Differential input and output
Flexible output and input common-mode ranges
Optional dc offset compensation loop
SPI programmable filter corners and gain steps
Power-down feature
Single 3.3 V supply operation
APPLICATIONS
Baseband IQ receivers
Diversity receivers
ADC drivers
Point-to-point and point-to-multipoint radio
Instrumentation
Medical
GENERAL DESCRIPTION
The ADRF6516 is a matched pair of fully differential, low noise
and low distortion programmable filters and variable gain
amplifiers (VGAs). Each channel is capable of rejecting large
out-of-band interferers while reliably boosting the desired signal,
thus reducing the bandwidth and resolution requirements on the
analog-to-digital converters (ADCs). The excellent matching
between channels and their high spurious-free dynamic range
over all gain and bandwidth settings make the ADRF6516 ideal
for quadrature-based (IQ) communication systems with dense
constellations, multiple carriers, and nearby interferers.
The filters provide a six-pole Butterworth response with 1 dB
corner frequencies programmable through the SPI port from
1 MHz to 31 MHz in 1 MHz steps. The preamplifier that precedes
the filters offers a SPI-programmable option of either 3 dB or 6 dB
of gain. The preamplifier sets a differential input impedance of
1600 Ω and has a common-mode voltage that defaults to VPS/2
but can be driven from 1.1 V to 1.8 V.
FUNCTIONAL BLOCK DIAGRAM
ENBL INP1 INM1 VPS COM VICM OFS1 VPS
VPSD
COMD
LE
CLK
DATA
SDO
COM
VPS
SPI
ADRF6516
OPP1
OPM1
COM
GAIN
VOCM
COM
OPM2
OPP2
COM INP2 INM2 VPS COM OFDS OFS2 VPS
Figure 1.
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The variable gain amplifiers that follow the filters provide 50 dB
of continuous gain control with a slope of 15.5 mV/dB. Their
maximum gains can be programmed to various values through
the SPI. The output buffers provide a differential output impedance
of 30 Ω and are capable of driving 2 V p-p into 1 kΩ loads. The
output common-mode voltage defaults to VPS/2, but it can be
adjusted down to 700 mV by driving the high impedance VOCM
pin. Independent, built-in dc offset compensation loops can be
disabled if fully dc-coupled operation is desired. The high-pass
corner frequency is defined by external capacitors on the OFS1
and OFS2 pins and the VGA gain.
The ADRF6516 operates from a 3.15 V to 3.45 V supply
and consumes a maximum supply current of 360 mA when
programmed to the highest bandwidth setting. When disabled,
it consumes <9 mA. The ADRF6516 is fabricated in an advanced
silicon-germanium BiCMOS process and is available in a 32-lead,
exposed paddle LFCSP. Performance is specified over the −40°C
to +85°C temperature range.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
datasheet pdf - http://www.DataSheet4U.net/
1 page  
Data Sheet
TIMING DIAGRAMS
ADRF6516
tCLK
tPW
CLK
tLS
tLH
LE
tDS tDH
DATA
WRITE BIT
LSB
B2
B3
B4
B5
B6
B7 MMSBSB - 2
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A WRITE
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 8-BIT WORD IS THEN WRITTEN TO THE DATA PIN ON CONSECUTIVE RISING
EDGES OF THE CLOCK.
Figure 2. Write Mode Timing Diagram
CLK
LE
DATA
tD
tLS
tCLK
tPW
tLH
tDS tDH
READ BIT DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’DTOCNA'TRECARDEON’T CARE
SDO
LSB
B2
B3 B4
B5
B6 B7 MSB
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A READ
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE 8-BIT WORD IS THEN REGISTERED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES
OF THE CLOCK.
Figure 3. Read Mode Timing Diagram
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Rev. B | Page 5 of 32
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5 Page 
Data Sheet
80
GAIN = 0dB, HD2
GAIN = 0dB, HD3
GAIN = 10dB, HD2
75 GAIN = 10dB, HD3
70
65
60
55
50
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
VICM (V)
Figure 23. HD2 and HD3 vs. Input Common-Mode Voltage
(Bandwidth Setting = 31 MHz, 0.4 V p-p Input Level)
45
BANDWIDTH = 31MHz
f1 = 14MHz, f2 = 15MHz
40
DIGITAL GAIN = 000
35
DIGITAL GAIN = 111
30
25
20
15
10
5
0
0 5 10 15 20 25 30 35 40 45 50
GAIN (dB)
Figure 24. In-Band OIP3 vs. Gain (Bandwidth Setting = 31 MHz)
45
BANDWIDTH = 31MHz
40
f1 = 14MHz, f2 = 15MHz
DIGITAL GAIN = 111
35
30
–40°C
+85°C
+25°C
25
20
15
10
5
0
0 5 10 15 20 25 30 35 40 45
GAIN (dB)
Figure 25. In-Band OIP3 vs. Gain over Temperature
(Bandwidth Setting = 31 MHz)
50
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ADRF6516
110
100
90
80
70
60
50 GAIN = 30dB
GAIN = 20dB
40 GAIN = 10dB
GAIN = 0dB
30
20
10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
COMPOSITE OUTPUT VOLTAGE (V p-p)
4.0
Figure 26. In-Band Third-Order Intermodulation Distortion
(Bandwidth Setting = 31 MHz, Digital Gain = 000)
100
90
80
70
60
50
40
GAIN = 40dB
30 GAIN = 30dB
GAIN = 20dB
20 GAIN = 10dB
GAIN = 0dB
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
COMPOSITE OUTPUT VOLTAGE (V p-p)
Figure 27. In-Band Third-Order Intermodulation Distortion
(Bandwidth Setting = 31 MHz, Digital Gain = 111)
70
60
50 BANDWIDTH = 31MHz
40
30
20
10
0
–10
–20
–30 2:1 SLOPE
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
OUT-OF-BAND IIP2
–140
–150
PREAMP GAIN = 6dB
–160
PREAMP GAIN = 3dB
–170
–55 –45 –35 –25 –15 –5 5 15 25 35 45 55
INPUT LEVEL AT 115MHz AND 130MHz (dBV/TONE)
Figure 28. Out-of-Band IIP2, IMD2 Tone at Midband
(Bandwidth Setting = 31 MHz)
65
Rev. B | Page 11 of 32
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| PDF Descargar | [ Datasheet ADRF6516.PDF ] | |
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