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DAC1627D1G25 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer DAC1627D1G25
Beschreibung Dual 16-bit DAC
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
DAC1627D1G25 Datasheet, Funktion
DAC1627D1G25
Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and
x8 interpolating
Rev. 1 — 29 April 2011
Objective data sheet
1. General description
The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter
(DAC) with selectable ×2, ×4 and ×8 interpolating filters optimized for multi-carrier and
broadband wireless transmitters at sample rates of up to 1.25 Gsps. Supplied from a
3.3 V and a 1.8 V source, the DAC1627D1G25 integrates a differential scalable output
current up to 31.8 mA.
The DAC1627D1G25 is capable of meeting multi-carrier GSM specifications. For
example, with an output frequency of 150 MHz and a DAC clock frequency of 1.22 Gsps
the full-scale dynamic range is:
SFDRRBW = 85 dBc (bandwidth = 250 MHz)
IMD3 = 85 dBc
The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25.
The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data
Rate (DDR) receiver interface, with an on-chip 100 Ω termination. The LVDS DDR
interface accepts a multiplex input data stream such as interleaved or folded. An internal
LVDS input auto-calibration ensures the robustness and stability of the interface.
http://www.DataSheet4U.net/
Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. The
mixer frequency is set by a 40-bit Numerically Controlled Oscillator (NCO). High resolution
internal gain, phase and offset control provide outstanding image and Local Oscillator
(LO) signal rejection at the system analog modulator output.
An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at
the DAC output.
Multiple device synchronization allows synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
The DAC1627D1G25 includes a very low noise capacitor-free integrated Phase-Locked
Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.
The DAC1627D1G25 is available in a HVQFN72 package (10 mm × 10 mm).
datasheet pdf - http://www.DataSheet4U.net/






DAC1627D1G25 Datasheet, Funktion
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 2. Pin description …continued
Symbol
Pin Type[1] Description
SDIO
51 IO SPI data input/output
SCLK
52 I
SPI clock
SCS_N
53 I
SPI chip select (active LOW)
RESET_N
54
I
general reset (active LOW)
VDDA(1V8)_D
IOUTBN
55
56
P
O
1.8 V analog power supply (DAC core)
complementary DAC B output current
IOUTBP
57 O
DAC B output current
VDDA(1V8)_D
VDDA(3V3)
AUXBP
58
59
60
P
P
O
1.8 V analog power supply (DAC core)
3.3 V analog power supply
auxiliary DAC B output current
AUXBN
61 O
complementary auxiliary DAC B output current
VDDA(1V8)_P1
62
P
1.8 V analog power supply (PLL)
VIRES
63 IO DAC biasing resistor
GAPOUT
64 IO
band gap input/output voltage
VDDA(1V8)_P2
AUXAN
65
66
P
O
1.8 V analog power supply (PLL)
complementary auxiliary DAC A output current
AUXAP
67 O
auxiliary DAC A output current
VDDA(3V3)
68 P
VDDA1V8_D 69 P
IOUTAP
70 O
3.3 V analog power supply
1.8 V analog power supply (DAC core)
DAC A output currenthttp://www.DataSheet4U.net/
IOUTAN
71 O
complementary DAC A output current
VDDA(1V8)_D
GND
72
H
P
G
1.8 V analog power supply (DAC core)
ground (exposed die pad)
[1] P: power supply; G: ground; I: input; O: output.
[2] The LVDS input data bus order can be reversed and each element can be swapped between P and N using
dedicated registers (see Table 86, Table 87 and Table 88).
7. Limiting values
DAC1627D1G25
Objective data sheet
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VDDA(3V3) analog supply voltage
(3.3 V)
0.5
VDDD(1V8) digital supply voltage
(1.8 V)
0.5
VDDA(1V8) analog supply voltage
(1.8 V)
[1] 0.5
VI input voltage
VO output voltage
input pins referenced to GND
pins IOUTAP, IOUTAN,
IOUTBP, IOUTBN, AUXAP,
AUXAN, AUXBP and AUXBN
referenced to GND
0.5
0.5
Max
+4.6
Unit
V
+2.5 V
+2.5 V
<tbd> V
+4.6 V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
6 of 69
datasheet pdf - http://www.DataSheet4U.net/

6 Page









DAC1627D1G25 pdf, datenblatt
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 5. Characteristics …continued
VDDA(1V8) = 1.8 V; VDDD(1V8) = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 22; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
[1]
Min
Typ
Max Unit
ACPR
NSD
adjacent channel
power ratio
fs = 1228.8 Msps;
×4 interpolation;
fo = 210 MHz
1 carrier; BW = 5 MHz
2 carriers; BW = 10 MHz
4 carriers; BW = 20 MHz
noise spectral
density
fs = 983.04 Msps;
×4 interpolation;
fo = 20 MHz at 1 dBFS
fs = 983.04 Msps;
×4 interpolation;
fo = 153.6 MHz at 1 dBFS
D
D
D
D
D
-
-
-
-
-
77
73
72
-164
-161
-
-
-
-
-
dBc
dBc
dBc
dBm/Hz
dBm/Hz
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] VDDA(1V8)_D, VDDA(1V8)_P1 and VDDA(1V8)_P2 must be connected to the same 1.8 V analog power supply. it is recommended to use
dedicated filters for the three power pins.
[3] |Vgpd| represents the ground potential difference voltage. This voltage is the result of current flowing through the finite resistance and the
inductance between the receiver and the driver circuit ground voltages.
10. Application information
http://www.DataSheet4U.net/
10.1 General description
The DAC1627D1G25 is a dual 16-bit DAC operating up to 1250 Msps. Each DAC consists
of a segmented architecture, comprising a 6-bit thermometer sub-DAC and a 10-bit binary
weighted sub-DAC.
A maximum input LVDS DDR data rate of up to 312.5 MHz and a maximum output
sampling rate of 1250 Msps ensure more flexibility for wide bandwidth and multi-carrier
systems. The internal 40-bit NCO of the DAC1627D1G25 simplifies the frequency
selection of the system. The DAC1627D1G25 provides ×2, ×4 or ×8 interpolation filters
that are very useful for removing the undesired images.
Each DAC generates two complementary current outputs on pins IOUTAP and IOUTAN
and pins IOUTBP and IOUTBN. These outputs provide a full-scale output current (IO(fs)) of
up to 31.8 mA. An internal reference is available for the reference current which is
externally adjustable using pin VIRES.
High resolution internal gain, phase and offset control provide outstanding image and
Local Oscillator (LO) signal rejection at the system analog modulator output.
Multiple device synchronization enables synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
All functions can be set using an SPI interface.
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
12 of 69
datasheet pdf - http://www.DataSheet4U.net/

12 Page





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