Datenblatt-pdf.com


GS8342T18GE-167 Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8342T18GE-167
Beschreibung (GS8342Txxx) 36Mb SigmaCIO DDR-II Burst of 2 SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8342T18GE-167 Datasheet, Funktion
Preliminary
GS8342T08/09/18/36E-333/300/267*/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
36Mb SigmaCIO DDR-II
Burst of 2 SRAM
167 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb
and 144Mb devices
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
SigmaCIOFamily Overview
The GS8342T08/09/18/36E are built in compliance with the
SigmaCIO DDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342T08/09/18/36E SigmaCIO SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342T08/09/18/36E SigmaCIO DDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
http://www.DataSheet4U.net/
Common I/O x36 and x18 SigmaCIO DDR-II B2 RAMs
always transfer data in two packets. When a new address is
loaded, A0 presets an internal 1 bit address counter. The
counter increments by 1 (toggles) for each beat of a burst of
two data transfer.
Common I/O x8 SigmaCIO DDR-II B2 RAMs always transfer
data in two packets. When a new address is loaded, the LSB
is internally set to 0 for the first read or write transfer, and
incremented by 1 for the next transfer. Because the LSB is
tied off internally, the address field of a x8 SigmaCIO DDR-II
B4 RAM is always one address pin less than the advertised
index depth (e.g., the 8M x 8 has a 2M addressable index).
tKHKH
tKHQV
Parameter Synopsis
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-267*
3.75 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
* The 267 MHz speed bin is only available on the x18 part.
Rev: 1.02 8/2005
1/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
datasheet pdf - http://www.DataSheet4U.net/






GS8342T18GE-167 Datasheet, Funktion
Preliminary
GS8342T08/09/18/36E-333/300/267*/250/200/167
Pin Description Table
Symbol
SA
NC
R/W
BW0–BW3
Description
Synchronous Address Inputs
No Connect
Synchronous Read/Write
Synchronous Byte Writes
NW0–NW1
Nybble Write Control Pin
LD Synchronous Load Pin
K Input Clock
K Input Clock
C Output Clock
C Output Clock
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock Input
TDO Test Data Output
VREF
ZQ
HSTL Input Reference Voltage
http://www.DataSheet4U.net/
Output Impedance Matching Input
DQ Data I/O
Doff Disable DLL when low
CQ Output Echo Clock
CQ Output Echo Clock
VDD Power Supply
VDDQ
Isolated Output Buffer Supply
VSS Power Supply: Ground
Note:
NC = Not Connected to die or any other pin
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input/Output
Input
Output
Output
Supply
Supply
Supply
Comments
Active Low
x18/x36 only
Active Low
x8 only
Active Low
Active High
Active Low
Active High
Active Low
Three State
Active Low
1.8 V Nominal
1.5 V Nominal
Rev: 1.02 8/2005
6/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
datasheet pdf - http://www.DataSheet4U.net/

6 Page









GS8342T18GE-167 pdf, datenblatt
Preliminary
GS8342T08/09/18/36E-333/300/267*/250/200/167
B2 Nybble Write Clock Truth Table
NW NW
Current Operation
K
(tn+1)
K
(tn+2)
K
(tn)
TT
Write
Dx stored if NWn = 0 in both data transfers
TF
Write
Dx stored if NWn = 0 in 1st data transfer only
FT
Write
Dx stored if NWn = 0 in 2nd data transfer only
FF
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
D
K
(tn+1)
D1
D1
X
X
D
K
(tn+2)
D2
X
D2
X
http://www.DataSheet4U.net/
*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.
Rev: 1.02 8/2005
12/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
datasheet pdf - http://www.DataSheet4U.net/

12 Page





SeitenGesamt 30 Seiten
PDF Download[ GS8342T18GE-167 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
GS8342T18GE-167(GS8342Txxx) 36Mb SigmaCIO DDR-II Burst of 2 SRAMGSI Technology
GSI Technology
GS8342T18GE-167I(GS8342Txxx) 36Mb SigmaCIO DDR-II Burst of 2 SRAMGSI Technology
GSI Technology

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche