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PCAL9535A Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCAL9535A
Beschreibung Low-voltage 16-bit I2C-bus I/O port
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCAL9535A Datasheet, Funktion
PCAL9535A
Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O
Rev. 2 — 23 January 2015
Product data sheet
1. General description
The PCAL9535A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander
with interrupt and reset for I2C-bus/SMBus applications. NXP I/O expanders provide a
simple solution when additional I/Os are needed while keeping interconnections to a
minimum, for example, in ACPI power switches, sensors, push buttons, LEDs, fan control,
etc.
In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V
allows the PCAL9535A to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCAL9535A contains the PCA9535 register set of four pairs of 8-bit Configuration,
Input, Output, and Polarity Inversion registers, and additionally, the PCAL9535A has
Agile I/O, which are additional features specifically designed to enhance the I/O. These
additional features are: programmable output drive strength, latchable inputs,
programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,
programmable open-drain or push-pull outputs.
The PCAL9535A is a pin-to-pin replacement to the PCA9535 and PCA9535A, however,
the PCAL9535A powers up with all I/O interrupts masked. This mask default allows for a
board bring-up free of spurious interrupts at power-up.
The PCAL9535A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C-bus. Thus, the PCAL9535A can
remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine.
Three hardware pins (A0, A1, A2) select the fixed I2C-bus address and allow up to eight
devices to share the same I2C-bus/SMBus.






PCAL9535A Datasheet, Funktion
NXP Semiconductors
PCAL9535A
Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O
B7 B6 B5 B4 B3 B2 B1 B0
002aaf540
Fig 5. Pointer register bits
Table 4. Command byte
Pointer register bits
Command byte Register
B7 B6 B5 B4 B3 B2 B1 B0 (hexadecimal)
Protocol
Power-up
default
00000000
00h Input port 0
read byte
xxxx xxxx[1]
00000001
01h Input port 1
read byte
xxxx xxxx
00000010
02h Output port 0
read/write byte 1111 1111
00000011
03h Output port 1
read/write byte 1111 1111
00000100
04h Polarity Inversion port 0 read/write byte 0000 0000
00000101
05h Polarity Inversion port 1 read/write byte 0000 0000
00000110
06h
Configuration port 0
read/write byte 1111 1111
00000111
07h
Configuration port 1
read/write byte 1111 1111
01000000
40h
Output drive strength
read/write byte 1111 1111
register 0
01000001
41h
Output drive strength
read/write byte 1111 1111
register 0
01000010
42h
Output drive strength
read/write byte 1111 1111
register 1
01000011
43h
Output drive strength
read/write byte 1111 1111
register 1
01000100
44h
Input latch register 0
read/write byte 0000 0000
01000101
45h
Input latch register 1
read/write byte 0000 0000
01000110
46h Pull-up/pull-down enable read/write byte 0000 0000
register 0
01000111
47h Pull-up/pull-down enable read/write byte 0000 0000
register 1
01001000
48h Pull-up/pull-down
read/write byte 1111 1111
selection register 0
01001001
49h Pull-up/pull-down
read/write byte 1111 1111
selection register 1
01001010
4Ah Interrupt mask register 0 read/write byte 1111 1111
01001011
4Bh Interrupt mask register 1 read/write byte 1111 1111
01001100
4Ch Interrupt status register 0 read byte 0000 0000
01001101
4Dh Interrupt status register 1 read byte 0000 0000
01001111
4Fh Output port configuration read/write byte 0000 0000
register
[1] Undefined.
PCAL9535A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 23 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 46

6 Page









PCAL9535A pdf, datenblatt
NXP Semiconductors
PCAL9535A
Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O
6.2.11 Interrupt status register pair (4Ch, 4Dh)
These read-only registers are used to identify the source of an interrupt. When read, a
logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0
indicates that the input pin is not the source of an interrupt.
When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt
status bit will return logic 0. A register pair write is described in Section 7.1 and a register
pair read is described in Section 7.2.
Table 25.
Bit
Symbol
Default
Interrupt status port 0 register (address 4Ch) bit description
765432
S0.7
S0.6
S0.5
S0.4
S0.3
S0.2
000000
1
S0.1
0
0
S0.0
0
Table 26.
Bit
Symbol
Default
Interrupt status port 1 register (address 4Dh) bit description
765432
S1.7
S1.6
S1.5
S1.4
S1.3
S1.2
000000
1
S1.1
0
0
S1.0
0
6.2.12 Output port configuration register (4Fh)
The output port configuration register selects port-wise push-pull or open-drain I/O stage.
A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 6). A logic 1
configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended
command sequence to program this register (4Fh) before the configuration registers (06h,
07h) sets the port pins as outputs.
ODEN0 configures Port 0_x and ODEN1 configures Port 1_x.
Table 27. Output port configuration register (address 4Fh)
Bit 7 6 5 4 3 2 1 0
Symbol
reserved
ODEN1 ODEN0
Default
0
0
0
0
0
0
0
0
PCAL9535A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 23 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 46

12 Page





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