Datenblatt-pdf.com


AD9550 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9550
Beschreibung Integer-N Clock Translator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD9550 Datasheet, Funktion
Integer-N Clock Translator
for Wireline Communications
AD9550
FEATURES
Converts preset standard input frequencies to standard
output frequencies
Input frequencies from 8 kHz to 200 MHz
Output frequencies up to 810 MHz LVPECL and LVDS
(200 MHz CMOS)
Preset pin-programmable frequency translation ratios
On-chip VCO
Single-ended CMOS reference input
Two output clocks (independently programmable as LVDS,
LVPECL, or CMOS)
Single supply (3.3 V)
Very low power: <450 mW (under most conditions)
Small package size (5 mm × 5 mm)
Exceeds Telcordia GR-253-CORE jitter generation, transfer
and tolerance specifications
BASIC BLOCK DIAGRAM
REF
PLL
OUTPUT
CIRCUITRY
PIN DECODER
AD9550
Figure 1.
OUT2
OUT1
APPLICATIONS
Cost effective replacement of high frequency VCXO, OCXO,
and SAW resonators
Flexible frequency translation for wireline applications such
as Ethernet, T1/E1, SONET/SDH, GPON, xDSL
Wireless infrastructure
Test and measurement (including handheld devices)
www.DataSheet.net/
GENERAL DESCRIPTION
The AD9550 is a phase-locked loop (PLL) based clock translator
designed to address the needs of wireline communication and
base station applications. The device employs an integer-N PLL
to accommodate the applicable frequency translation requirements.
It accepts a single-ended input reference signal at the REF input.
The AD9550 is pin programmable, providing a matrix of
standard input/output frequency translations from a list of
15 possible input frequencies to a list of 52 possible output
frequency pairs (OUT1 and OUT2).
The AD9550 output is compatible with LVPECL, LVDS, or
single-ended CMOS logic levels, although the AD9550 is
implemented in a strictly CMOS process.
The AD9550 operates over the extended industrial temperature
range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.co.kr/






AD9550 Datasheet, Funktion
AD9550
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage (VDD)
Maximum Digital Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
3.6 V
−0.5 V to VDD + 0.5 V
−65°C to +150°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
www.DataSheet.net/
Rev. 0 | Page 6 of 20
Datasheet pdf - http://www.DataSheet4U.co.kr/

6 Page









AD9550 pdf, datenblatt
AD9550
THEORY OF OPERATION
LOCKED
FILTER
REF
LOCK
DETECT
×2 1
÷R
0
÷5 1
14
0 ×2 R
÷5 ÷5, ×2, R
PLL 3350MHz TO
UP 4050MHz
CHARGE LOOP
PUMP FILTER
VCO
DN
÷N
20
N
P0
3
P0
PRECONFIGURED
DIVIDER SETTINGS
N, P0, P1, P2
46
AD9550
2
P2
10
P2
P1
2
10
P1
OUTPUT
MODE
CONTROL
3
OUT2
OUT1
OM2 TO
OM0
A3 TO A0 Y5 TO Y0
Figure 23. Detailed Block Diagram
OVERVIEW
The AD9550 accepts one input reference clock, REF. The input
clock path includes an optional divide-by-5 prescaler, an optional
×2 frequency multiplier, and a 14-bit programmable divider (R).
The output of the R divider drives the input to the PLL.
The PLL translates the R-divider output to a frequency within
the operating range of the VCO (3.35 GHz to 4.05 GHz) based
on the value of the feedback divider (N). The VCO prescaler (P0)
reduces the VCO output frequency by an integer factor from 5 to 11,
resulting in an intermediate frequency in the range of 305 MHz
to 810 MHz. The 10-bit P1 and P2 dividers can further reduce
the P0 output frequency to yield the final output clock frequencies
at OUT1 and OUT2, respectively.
Thus, the frequency translation ratio from the reference input to
the output depends on the selection of the divide-by-5 prescalers,
the ×2 frequency multipliers, the values of the three R dividers,
the N divider, and the P0, P1, and P2 dividers. These parameters
are set automatically via the preconfigured divider settings per
the Ax and Yx pins (see the Preset Frequencies section).
PRESET FREQUENCIES
The frequency selection pins (A3 to A0 and Y5 to Y0) allow the
user to hardwire the device for preset input and output frequencies
based on the pin logic states (see Figure 23). The pins decode
ground or open connections as Logic 0 or Logic 1, respectively.
The A3 to A0 pins allow the user to select one of 15 input
reference frequencies as shown in Table 6. The device sets the
appropriate divide-by-5 (÷5), multiply-by-2 (×2), and input divider
(R)www.DataSheet.net/ values based on the logic levels applied to the Ax pins.
The divide-by-5, ×2, and R values cause the PLL input frequency
to be either 16 kHz or 40/3 kHz. There are two exceptions. The
first is for A3 to A0 = 1101, which yields a PLL input frequency
of 155.52/59 MHz. The second is for A3 to A0 = 1110, which
yields a PLL input frequency of either 1.5625 MHz or 4.86 MHz
depending on the Y5 to Y0 pins.
The Y5 to Y0 pins allow the user to select one of 52 output frequency
combinations (fOUT1 and fOUT2) per Table 7. The device sets the
appropriate P0, P1, and P2 settings based on the logic levels applied
to the Yx pins. Note, however, that selecting 101101 through
110010 require A3 to A0 = 1101 and selecting 110011 requires
A3 to A0 = 1110.
The value (N) of the PLL feedback divider and the control
setting for the charge pump current (CP) depend on a combi-
nation of both the Ax and Yx pin settings as shown in Table 8.
Rev. 0 | Page 12 of 20
Datasheet pdf - http://www.DataSheet4U.co.kr/

12 Page





SeitenGesamt 20 Seiten
PDF Download[ AD9550 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD9550Integer-N Clock TranslatorAnalog Devices
Analog Devices
AD9551Multiservice Clock GeneratorAnalog Devices
Analog Devices
AD9552Oscillator Frequency Up ConverterAnalog Devices
Analog Devices
AD9553Flexible Clock TranslatorAnalog Devices
Analog Devices
AD9554Multiservice Line Card Adaptive Clock TranslatorAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche