PDF AD9525 Data sheet ( Hoja de datos )

Número de pieza	AD9525
Descripción	Low Jitter Clock Generator
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet FEATURES Integrated ultralow noise synthesizer 8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC output or 2 CMOS SYNC outputs 2 differential reference inputs and 1 single-ended reference input APPLICATIONS LTE and multicarrier GSM base stations Clocking high speed ADCs, DACs ATE and high performance instrumentation 40/100 Gb/sec OTN line side clocking Cable/DOCSIS CMTS clocking Test and measurement GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be used with an external VCO or VCXO. The VCO input and eight LVPECL outputs can operate up to a frequency of 3.6 GHz. All outputs share a common divider that can provide a division of 1 to 6. Low Jitter Clock Generator with Eight LVPECL Outputs AD9525 REFA REFA REFB REFB REFC CLKIN CLKIN FUNCTIONAL BLOCK DIAGRAM AD9525 PLL ÷S DIVIDERS SPI CONTROL Figure 1. SYNC_OUT SYNC_OUT OUT7 OUT7 OUT6 OUT6 OUT5 OUT5 OUT4 OUT4 OUT3 OUT3 OUT2 OUT2 OUT1 OUT1 OUT0 OUT0 The AD9525 offers a dedicated output that can be used to provide a programmable signal for resetting or synchronizing a data converter. The output signal is activated by a SPI write. The AD9525 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. The external VCXO or VCO can have an operating voltage of up to 5.5 V. The AD9525 operates over the extended industrial temperature range of −40°C to +85°C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD9525 Data Sheet Parameter POWER DELTAS, INDIVIDUAL FUNCTIONS M Divider On/Off P Divider On/Off B Divider On/Off REFB On PLL On/Off One Channel, One Driver One Channel, Two Drivers Min Typ 5 3 16 15 254 107 184 REFA AND REFB INPUT CHARACTERISTICS Table 4. Parameter DIFFERENTIAL MODE (REFA, REFA; REFB, REFB) Min Typ Input Frequency 0 Input Sensitivity Self-Bias Voltage, REFA and REFB Self-Bias Voltage, REFA and REFB Input Resistance, REFA and REFB Input Resistance, REFA and REFB DUTY CYCLE 200 1.52 1.65 1.38 1.50 4.5 4.7 4.9 5.2 Pulse Width Low Pulse Width High 500 500 Max Unit 8.7 5.7 23.1 25 300.5 mW mW mW mW mW 132 mW 233 mW Test Conditions/Comments Power delta when a function is enabled/disabled M divider bypassed P divider bypassed B divider bypassed Delta from powering down REFB differential input PLL off to PLL on, normal operation; no reference enabled No LVPECL output on to one LVPECL output on at 2949.12 MHz; same output pair No LVPECL output on to two LVPECL outputs on at 2949.12 MHz; same output pair Max Unit Test Conditions/Comments Differential mode (can accommodate single- ended input by ac grounding unused input) 500 MHz Frequencies below ~1 MHz should be dc-coupled; be careful to match self-bias voltage mV p-p Frequency at 122.88 MHz 1.78 V Self-bias voltage of REFA and REFB inputs1 1.61 V Self-bias voltage of REFA and REFB inputs1 4.9 kΩ Self-biased1 5.4 kΩ Self-biased1 Duty cycle bounds are set by pulse width high and pulse width low ps ps 1 The differential pairs of REFA and REFA, REFB and REFB self-bias points are offset slightly to avoid chatter on an open input condition. REFC INPUT CHARACTERISTICS Table 5. Parameter REFC INPUT Input Frequency Range Input High Voltage Input Low Voltage Input Current Duty Cycle Pulse Width Low Pulse Width High Min Typ Max Unit 2.0 1 300 MHz V 0.8 V µA 1 ns 1 ns Test Conditions/Comments DC-coupled input (not self-biased) Duty cycle bounds are set by pulse width high and pulse width low Rev. A \| Page 4 of 48 5 Page AD9525 Parameter CLK = 1474.56 MHz, FOUT = 1474.56 MHz Divider = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 800 kHz Offset At 1 MHz Offset At 10 MHz Offset CLK = 122.88 MHz, FOUT = 122.88 MHz Divider = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 800 kHz Offset At 1 MHz Offset At 10 MHz Offset PD, RESET, AND REF_SEL PINS Table 17. Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current PD, RESET Logic 0 Current REF_SEL Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming STATUS AND REF_MON PINS Table 18. Parameter OUTPUT CHARACTERISTICS Output Voltage High, VOH Output Voltage Low, VOL MAXIMUM TOGGLE RATE Min Typ Max Unit Test Conditions/Comments Data Sheet −114 −125 −134 −144 −149 −151 −151 −154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −134 −145 −153 −159 −161 −161 −161 −161 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Min Typ Max Unit 2.0 0.8 1 −112 V V µA µA 1 2 50 100 µA pF ns ns Test Conditions/Comments The minus sign indicates that current is flowing out of the AD9525, which is due to the internal pull-up resistor Min Typ 2.7 200 Max Unit V 0.4 V MHz Test Conditions/Comments 1 mA output load Applies when mux is set to any divider or counter output or PFD up/down pulse; usually debug mode only; beware that spurs can couple to output when any of these pins is toggling Rev. A \| Page 10 of 48 11 Page

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