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AD9739 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9739
Beschreibung RF Digital-to-Analog Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9739 Datasheet, Funktion
Data Sheet
FEATURES
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix mode
Industry leading single/multicarrier IF or RF synthesis
fOUT = 350 MHz, ACLR =80 dBc
fOUT = 950 MHz, ACLR = 78 dBc
fOUT = 2100 MHz, ACLR = 69 dBc
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Pin-compatible with the AD9739A
Multichip synchronization capability
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.16 W at 2.5 GSPS
APPLICATIONS
Broadband communications systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9739 is a 14-bit, 2.5 GSPS high performance RF digital-
to-analog converter (DAC) capable of synthesizing wideband
signals from dc up to 3.0 GHz. Its DAC core features a quad-
switch architecture that provides exceptionally low distortion
performance with an industry-leading direct RF synthesis
capability. This feature enables multicarrier generation up to
the Nyquist frequency in baseband mode as well as second and
third Nyquist zones in mix mode. The output current can be
programmed over the 8.66 mA to 31.66 mA range.
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. Multichip synchronization is possible
with an on-chip synchronization controller. A serial peripheral
interface (SPI) is used for device configuration as well as readback
of status registers.
The AD9739 is manufactured on a 0.18 μm CMOS process and
operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball
chip scale ball grid array for reduced package parasitics.
14-Bit, 2.5 GSPS,
RF Digital-to-Analog Converter
AD9739
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
SDIO
SDO
CS
SCLK
AD9739
1.2V
SPI DAC BIAS
VREF
I120
IOUTP
DCI
TxDAC
CORE
IOUTN
DCO
SYNC_OUT
SYNC_IN
CLK DISTRIBUTION
(DIV-BY-4)
SYNC-
CONTROLLER
Figure 1.
DACCLK
PRODUCT HIGHLIGHTS
1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix
mode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
5. A multichip synchronization capability.
6. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9739 Datasheet, Funktion
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA.
Table 1.
Parameter
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current
Output Compliance Range
Common-Mode Output Resistance
Differential Output Resistance
Output Capacitance
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
DAC Clock Rate
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
VDDA
VDDC
DIGITAL SUPPLY VOLTAGES
VDD33
VDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS
IVDDA
IVDDC
IVDD33
IVDD
Power Dissipation
Sleep Mode, IVDDA
Power-Down Mode (Register 0x01 = 0x33 and Register 0x02 = 0x80)
IVDDA
IVDDC
IVDD33
IVDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS
IVDDA
IVDDC
IVDD33
IVDD
Power Dissipation
Rev. C | Page 5 of 49
AD9739
Min Typ
14
Max Unit
Bits
±1.3 LSB
±0.8 LSB
5.5
8.66 20.2
−1.0
10
70
1
31.66
+1.0
%
mA
V
Ω
pF
1.2 1.6
2.0
900
0.8 2.5
V
mV
GHz
60 ppm/°C
20 ppm/°C
1.15 1.2
5
1.25 V
3.1 3.3
1.70 1.8
3.5 V
1.90 V
3.10 3.3
1.70 1.8
3.5 V
1.90 V
37
159
34
233
0.940
2.5
38
166
37
238
0.975
2.75
mA
mA
mA
mA
W
mA
0.02 mA
3.8 mA
0.5 mA
0.1 mA
37 mA
223 mA
34 mA
290 mA
1.16 W

6 Page









AD9739 pdf, datenblatt
Data Sheet
AD9739
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B I120
C VREF
D
E
F
G AD9739
H
IRQ
CS
SCLK
RESET
SDIO
SDO
J
K
L
M
N
P
Figure 6. Analog I/O and SPI Control Pins (Top View)
Table 7. AD9739 Pin Function Descriptions
Pin No.
Mnemonic
C1, C2, D1, D2, E1, E2, E3, E4
VDDC
A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,
C5, D4, D5
VSSC
A10, A11, B10, B11, C10, C11, D10, D11 VDDA
A12, A13, B12, B13, C12, C13, D12, D13, VSSA
A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3,
F4, E11, E12, E13, E14, F11, F12
VSSA Shield
A14 NC
A7, B7, C7, D7
IOUTN
A8, B8, C8, D8
IOUTP
B14 I120
C14 VREF
D14
C3, D3
F13
NC
DACCLK_N/DACCLK_P
IRQ
F14
G13
G14
H13
H14
J3, J4, J11, J12
G1, G2, G3, G4, G11, G12
H1, H2, H3, H4, H11, H12, K3, K4, K11, K12
J1, J2
K1, K2
J13, J14
K13, K14
L1, M1
L2, M2
L3, M3
RESET
CS
SDIO
SCLK
SDO
VDD33
VDD
VSS
SYNC_OUT_P/SYNC_OUT_N
SYNC_IN_P/SYNC_IN_N
DCO_P/DCO_N
DCI_P/DCI_N
DB1[0]P/DB1[0]N
DB1[1]P/DB1[1]N
DB1[2]P/DB1[2]N
Description
1.8 V Clock Supply Input.
Clock Supply Return.
3.3 V Analog Supply Input.
Analog Supply Return.
Analog Supply Return Shield. Tie to VSSA at the DAC.
No Connect. Do not connect to this pin.
DAC Negative Current Output Source.
DAC Positive Current Output Source.
Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ
resistor to generate a 120 μA reference current.
Voltage Reference Input/Output. Decouple to VSSA with a
1 nF capacitor.
Factory Test Pin. Do not connect to this pin.
Negative/Positive DAC Clock Input (DACCLK).
Interrupt Request Open Drain Output. Active high. Pull up to
VDD33 with a 10 kΩ resistor.
Reset Input. Active high. Tie to VSS if unused.
Serial Port Enable Input.
Serial Port Data Input/Output.
Serial Port Clock Input.
Serial Port Data Output.
3.3 V Digital Supply Input.
1.8 V Digital Supply. Input.
Digital Supply Return.
Positive/Negative SYNC Output (SYNC_OUT)
Positive/Negative SYNC Input (SYNC_IN)
Positive/Negative Data Clock Output (DCO).
Positive/Negative Data Clock Input (DCI).
Port 1 Positive/Negative Data Input Bit 0.
Port 1 Positive/Negative Data Input Bit 1.
Port 1 Positive/Negative Data Input Bit 2.
Rev. C | Page 11 of 49

12 Page





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