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PDF A4950 Data sheet ( Hoja de datos )
| Número de pieza | A4950 | |
| Descripción | Full-Bridge DMOS PWM Motor Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A4950
Full-Bridge DMOS PWM Motor Driver
Features and Benefits
• Low RDS(on) outputs
• Overcurrent protection (OCP)
▫ Motor short protection
▫ Motor lead short to ground protection
▫ Motor lead short to battery protection
• Low Power Standby mode
• Adjustable PWM current limit
• Synchronous rectification
• Internal undervoltage lockout (UVLO)
• Crossover-current protection
• Commercial temperature grade (A4950E: –40°C to 85°C )
• Automotive temperature grade (A4950K: –40°C to 125°C)
Package: 8-pin SOICN with exposed
thermal pad (suffix LJ)
Not to scale
Description
Designed for pulse width modulated (PWM) control of DC
motors, the A4950 is capable of peak output currents to ±3.5 A
and operating voltages to 40 V.
Input terminals are provided for use in controlling the speed and
direction of a DC motor with externally applied PWM control
signals. Internal synchronous rectification control circuitry is
provided to lower power dissipation during PWM operation.
Internal circuit protection includes overcurrent protection,
motor lead short to ground or supply, thermal shutdown with
hysteresis, undervoltage monitoring of VBB, and crossover-
current protection.
For high ambient operating temperature applications, an
automotive grade device is offered (A4950K). The K grade
device is tested across extended temperature and voltage
ranges to ensure compliance in automotive or industrial
applications.
The A4950 is provided in a low-profile 8-pin SOICN package
with exposed thermal pad (suffix LJ) that is lead (Pb) free, with
100% matte tin leadframe plating.
www.DataSheet.net/
Functional Block Diagram
IN1
IN2
GND
VREF
OSC
Charge
Pump
Control
Logic
Disable
TSD
UVLO
7V
÷ 10
Load Supply
VBB
OUT1
OUT2
LSS
(Optional)
A4950-DS, Rev. 3
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
A4950
Full-Bridge DMOS PWM Motor Driver
Functional Description
Device Operation
The A4950 is designed to operate DC motors. The output drivers
are all low-RDS(on) , N-channel DMOS drivers that feature inter-
nal synchronous rectification to reduce power dissipation. The
current in the output full bridge is regulated with fixed off-time
pulse width modulated (PWM) control circuitry. The IN1 and IN2
inputs allow two-wire control for the bridge.
Protection circuitry includes internal thermal shutdown, and pro-
tection against shorted loads, or against output shorts to ground
or supply. Undervoltage lockout prevents damage by keeping the
outputs off until the driver has enough voltage to operate nor-
mally.
Standby Mode
Low Power Standby mode is activated when both input (INx)
pins are low for longer than 1 ms. Low Power Standby mode
disables most of the internal circuitry, including the charge pump
and the regulator. When the A4950 is coming out of standby
mode, the charge pump should be allowed to reach its regulated
voltage (a maximum delay of 200 μs) before any PWM com-
mands are issued to the device.
Internal PWM Current Control
Initially, a diagonal pair of source and sink FET outputs are
enabled and current flows through the motor winding and the
optional external current sense resistor, RS. When the voltage
across RS equals the comparator trip value, then the current sense
comparator resets the PWM latch. The latch then turns off the
sink and source FETs (Mixed Decay mode).
VREF
The maximum value of current limiting is set by the selection of
RSx and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
ITripMAX (A), which is set by:
ITripMAX =
VREF
10 RS
where VREF is the input voltage on the VREF pin (V) and RS is
the resistance of the sense resistor (Ω) on the LSS terminal.
Overcurrent Protection
A current monitor will protect the IC from damage due to output
shorts. If a short is detected, the IC will latch the fault and disable
the outputs. The fault latch can only be cleared by coming out of
Low Power Standby mode or by cycling the power to VBB. Dur-
ing OCP events, Absolute Maximum Ratings may be exceeded
for a short period of time before the device latches.
Shutdown
If the die temperature increases to approximately 160°C, the full
bridge outputs will be disabled until the internal temperature falls
below
www.DataSheet.net/
a
hysteresis,
TTSDhys
,
of
15°C.
Internal
UVLO
is
present
on VBB to prevent the output drivers from turning-on below the
UVLO threshold.
Braking
The braking function is implemented by driving the device in
Slow Decay mode, which is done by applying a logic high to both
inputs, after a bridge-enable Chop command (see PWM Control
Truth Table). Because it is possible to drive current in both direc-
tions through the DMOS switches, this configuration effectively
shorts-out the motor-generated BEMF, as long as the Chop com-
mand is asserted. The maximum current can be approximated by
VBEMF / RL. Care should be taken to ensure that the maximum
ratings of the device are not exceeded in worse case braking situ-
ations: high speed and high-inertia loads.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page | ||
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| PDF Descargar | [ Datasheet A4950.PDF ] | |
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