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W25Q128BV Schematic ( PDF Datasheet ) - Winbond

Teilenummer W25Q128BV
Beschreibung 3V 128M-BIT SERIAL FLASH MEMORY
Hersteller Winbond
Logo Winbond Logo 




Gesamt 70 Seiten
W25Q128BV Datasheet, Funktion
W25Q128BV
3V 128M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
www.DataSheet.net/
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Publication Release Date: April 01, 2011
Revision E
Datasheet pdf - http://www.DataSheet4U.co.kr/






W25Q128BV Datasheet, Funktion
W25Q128BV
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W25Q128BV is offered in an 8-pad WSON 8x6-mm (package code E), a 16-pin SOIC 300-mil (package
code F) and a 24-ball 8x6-mm TFBGA (package code C) as shown in Figure 1a-c respectively. Package
diagrams and dimensions are illustrated at the end of this datasheet.
3.1 Pad Configuration WSON 8x6-mm
Top View
/CS 1 8 VCC
DO (IO1)
/WP (IO2)
GND
27
36
45
/HOLD (IO3)
CLK
DI (IO0)
Figure 1a. W25Q128BV Pad Assignments, 8-pad WSON 8x6-mm (Package Code E)
3.2 Pad Description WSON 8x6-mm
PAD NO.
PAD NAME
I/O
www.DataSheet.net/
FUNCTION
1 /CS I Chip Select Input
2
DO (IO1)
I/O Data Output (Data Input Output 1)*1
3
/WP (IO2)
I/O Write Protect Input ( Data Input Output 2)*2
4 GND
Ground
5
DI (IO0)
I/O Data Input (Data Input Output 0)*1
6 CLK I Serial Clock Input
7
/HOLD (IO3)
I/O Hold Input (Data Input Output 3)*2
8 VCC
Power Supply
*1: IO0 and IO1 are used for Standard and Dual SPI instructions
*2: IO0 – IO3 are used for Quad SPI instructions
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6 Page









W25Q128BV pdf, datenblatt
W25Q128BV
condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
Select (/CS) signal should be kept active low for the full duration of the /HOLD operation to avoid resetting
the internal logic state of the device.
6.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q128BV
provides several means to protect the data from inadvertent writes.
6.2.1 Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Status Register
Write Protection using Power-down instruction
Lock Down write protection until next power-up
One Time Program (OTP) write protection*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q128BV will maintainwww.DataSheet.net/ a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 38). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-
disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits. These
settings allow a portion as small as 4KB sector or the entire memory array to be configured as read only.
Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or
disabled under hardware control. See Status Register section for further information. Additionally, the
Power-down instruction offers an extra level of write protection as all instructions are ignored except for
the Release Power-down instruction.
- 12 -
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12 Page





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