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PDF CLAA150PB01 Data sheet ( Hoja de datos )

Número de pieza CLAA150PB01
Descripción Display Module
Fabricantes CHUNGHWA PICTURE TUBES 
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No Preview Available ! CLAA150PB01 Hoja de datos, Descripción, Manual

CPT
CHUNGHWA PICTURES TUBES, LTD.,
Chunghwa Picture Tubes, Ltd.
Technical Specification
To :
Date : 2004/9/16
CPT TFT-LCD
CLAA150PB01
ACCEPTED BY
www.DataSheet.net/
APPROVED BY
CHECKED BY
PREPARED BY
TFT-LCD
Product Planning
Management General Division
Prepared by : TFT-LCD Product Planning Management General Division
CHUNGHWA PICTURE TUBES, LTD.
1127 Hopin Rd., Padeh, Taoyuan, Taiwan 334, R.O.C.
TEL: +886-3-3675151 FAX: +886-3-377-3001
Doc.No:
CLAA150PB01--Ver.1-2004/9/16
Issue Date: 2004/9/16
T- 3650002- 000- A NEW
CPT Confidential
0/19
CLAA150PB01--VER.1- 2004/9/16
Datasheet pdf - http://www.DataSheet4U.co.kr/

1 page




CLAA150PB01 pdf
CPT
CHUNGHWA PICTURES TUBES, LTD.,
[Note 3]
When Test pattern is Black,this module Max. power consumption’s
condition :VCC=3.6 volts, Icc=850 mA,so when VCC=3.3 volts, Icc will be large than 850
mA (Black pattern),If driving condition VCC=3.0 volts ,Icc will be large than Vcc=3.3 volts.
[Note 4]
LVDS Signal definition :
VIN+
100 Ω
VIN-
LVDS Receiver
VIN-
VCM
VCM+
VID
VID = VIN+ - VIN-
VCM = | VCM+ - VCM- |
VID = | VID+ - VID- |
VID+ = | VIH+ - VIH- |
VID- = | VIL+ - VIL- |
VIN+
VIN+ = Positive differential DATA & CLK Input
VIN- = Negative differential DATA & CLK Input
VCM = ( VIN+ - VIN- ) / 2
VCM+ = ( VIH+ - VIH- ) / 2
VCM- = ( VIL+ - VIL- ) / 2
VIH-
VIL-
VIH+
VIL+
www.DataSheet.net/
(2) Backlight system
CPT Confidential
4/19
CLAA150PB01--VER.1- 2004/9/16
Datasheet pdf - http://www.DataSheet4U.co.kr/

5 Page





CLAA150PB01 arduino
CPT
CHUNGHWA PICTURES TUBES, LTD.,
ITEM
SYMBOL MIN TYP MAX UNIT
CLK frequency
fCLKin
-
54 57 MHz
CLK period
tCLKin 17.5
18.5
-
ns
LVDS High to Low transition time
LLHT
-
0.6 1.5 ns
LVDS Low to High transition time
LHLT
-
0.6 1.5 ns
LVDS Strobe position of Bit 0
Tdp0
-0.4
0
0.4 ns
Input Strobe position of Bit 1
Timing Strobe position of Bit 2
Tdp1 T/7-0.4 T/7 T/7+0.4
Tdp2 2T/7-0.4 2T/7 2T/7+0.4
ns
ns
Strobe position of Bit 3 f = 54MHz Tdp3 3T/7-0.4 3T/7 3T/7+0.4 ns
Strobe position of Bit 4
Tdp4 4T/7-0.4 4T/7 4T/7+0.4 ns
Strobe position of Bit 5
Tdp5 5T/7-0.4 5T/7 5T/7+0.4 ns
Strobe position of Bit 6
Tdp6 6T/7-0.4 6T/7 6T/7+0.4 ns
Horizontal Active Time
tHA 700 700 700 tCLK
Horizontal Front Porch
tHFP
2
24
- tCLK
LCD input
signal
DENA
Horizontal Back Porch
Vertical Active Time
Vertical Front Porch
tHBP
tVA
tVFP
4
1050
2
120
1050
3
-
1050
-
tCLK
tH
tH
Vertical Back Porch
tVBP
2
13
-
tH
( LVDS
Frequency
Tx Input , HD Period
Rx output )
Low width
fH - 63.98 69.51 kHz
tH 14.1 15.6 -
us
tWHL
1
56
- tCLK
Frequency
fV 55 60 62 Hz
VD Period
tV
16.1 16.7 18.2
ms
Low width
tWVL
1
3
- tH
[Note]
1) Polarities of HD and VD are negative in this specification.
2) DENA (Data Enable) should always be positive polarity as shown in the timing
specification.
3) CLKIN should appear during all invalid period, and HD should appear during invalid
period of frame cycle.
4) T(Period )= 1/f .
www.DataSheet.net/
CPT Confidential
10/19
CLAA150PB01--VER.1- 2004/9/16
Datasheet pdf - http://www.DataSheet4U.co.kr/

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