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ADuM7240 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADuM7240
Beschreibung (ADuM7240 / ADuM7241) Dual Channel Digital Isolators
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADuM7240 Datasheet, Funktion
Data Sheet
1 kV, Dual Channel Digital Isolators
ADuM7240/ADuM7241
FEATURES
Narrow-body, RoHS-compliant, 8-lead SOIC
Safety and regulatory approvals
UL recognition (pending)
UL 1577: 1000 V rms for 1 minute
Low power operation
5 V operation
2.4 mA per channel maximum at 0 Mbps to 1 Mbps
11.8 mA per channel maximum at 25 Mbps
3.3 V operation
1.7 mA per channel maximum at 0 Mbps to 1 Mbps
8.2 mA per channel maximum at 25 Mbps
Bidirectional communication
Up to 25 Mbps data rate (NRZ)
3 V/5 V level translation
High temperature operation: 105°C
High common-mode transient immunity: >15 kV/μs
APPLICATIONS
General-purpose multichannel isolation
Data converter isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM7240/ADuM72411 are dual channel digital isolators
based on the Analog Devices, Inc., iCoupler® technology.
Combining high speed CMOS and monolithic air core trans-
former technologies, these isolation components provide
outstanding performance characteristics superior to the alterna-
tives, such as optocoupler devices and other integrated couplers.
The ADuM7240/ADuM7241 dual 1 kV digital isolation devices
are packaged in a narrow-body 8-lead SOIC. The ADuM7240/
ADuM7241 offer a cost-effective option compared to 2.5 kV or
5 kV isolators where only functional isolation is needed.
Like other Analog Devices isolators, the ADuM7240/ADuM7241
offer very low power consumption, consuming one-tenth to
one-sixth the power of comparable isolators at data rates up to
25 Mbps. Despite the low power consumption, all models of the
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1
VIA 2
VIB 3
GND1 4
ENCODE
ENCODE
ADuM7240
DECODE
DECODE
Figure 1. ADuM7240
8 VDD2
7 VOA
6 VOB
5 GND2
VDD1 1
VOA 2
VIB 3
GND1 4
DECODE
ENCODE
ADuM7241
ENCODE
DECODE
Figure 2. ADuM7241
8 VDD2
7 VIA
6 VOB
5 GND2
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ADuM7240/ADuM7241 provide low pulse width distortion
(<5 ns for C grade). In addition, every model has an input glitch
filter to protect against extraneous noise disturbances.
The ADuM7240/ADuM7241 provide two independent
isolation channels and are available in two channel configura-
tions with 1 Mbps or 25 Mbps data rates (see the Ordering
Guide). All models operate with the supply voltage on either
side ranging from 3.0 V to 5.5 V, providing compatibility with
lower voltage systems as well as enabling voltage translation
functionality across the isolation barrier. The ADuM7240/
ADuM7241also have an output default high logic state in the
absence of input power.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/






ADuM7240 Datasheet, Funktion
ADuM7240/ADuM7241
Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V, VDD2 = 5 V. Minimum/maximum specifications apply over the entire recom-
mended operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10.
A Grade
C Grade
Parameter
Symbol Min Typ Max Min Typ Max Unit
Test
Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW 250
40
ns Within PWD limit
Data Rate
1 25 Mbps Within PWD limit
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
tPHL, tPLH
PWD
55 80
10 25
5
35 47 59
25
3
ns
ns
ps/°C
50% input to 50% output
|tPLH − tPHL|
Propagation Delay Skew1
Channel Matching
tPSK
20 10 ns
Codirectional
Opposing Direction
Jitter
tPSKCD
tPSKOD
25
30
2
25
ns
5 10 ns
2 ns
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
Table 11.
1 Mbps—A, C Grades
25 Mbps—C Grade
Parameter
Symbol Min
Typ
Max Min Typ Max Unit Test Conditions
SUPPLY CURRENT
ADuM7240
ADuM7241
IDD1
IDD2
IDD1
IDD2
1.6 1.9
11 14 mA
1.6
2.0
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2.9 3.4 mA
1.4 1.6
6.9 8.2 mA
1.9 2.3
8.4 10.2 mA
Table 12. For All Models
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Input Current per Channel
Supply Current per Channel
Quiescent Input Supply Current
Quiescent Output Supply Current
Dynamic Input Supply Current
Dynamic Output Supply Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity1
Refresh Rate
Symbol Min
VIH
VIL
VOH
VOL
II
IDDI(Q)
IDDO(Q)
IDDI(D)
IDDO(D)
tR/tF
|CM|
fr
0.7 VDDx
VDDx − 0.1
VDDx − 0.4
−10
15
Typ Max Unit
Test Conditions
VDDx
VDDx − 0.3
0.0
0.2
+0.01
0.3 VDDx
0.1
0.4
+10
V
V
V
V
V
V
µA
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0 V ≤ VIx ≤ VDDx
0.71 0.83 mA
0.80 0.90 mA
0.20 mA/Mbps
0.03 mA/Mbps
2.5 ns 10% to 90%
25
kV/µs
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
550 kHz DC data inputs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDx. The common-mode voltage slew rates apply to both
rising and falling common-mode voltage edges.
Rev. 0 | Page 6 of 16
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6 Page









ADuM7240 pdf, datenblatt
ADuM7240/ADuM7241
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD LAYOUT
The ADuM7240/ADuM7241 digital isolators require no
external interface circuitry for the logic interfaces. Power supply
bypassing is strongly recommended at both input and output
supply pins: VDD1 and VDD2. The capacitor value should be
between 0.01 μF and 0.1 μF. The total lead length between both
ends of the capacitor and the input power supply pin should not
exceed 20 mm.
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, users should design the board layout so that any
coupling that does occur affects all pins on a given component
side equally. Failure to ensure this can cause voltage differentials
between pins exceeding the absolute maximum ratings of the
device, thereby leading to latch-up or permanent damage.
With proper PCB design choices, the ADuM7240/ADuM7241
can readily meet CISPR 22 Class A (and FCC Class A)
emissions standards, as well as the more stringent CISPR 22
Class B (and FCC Class B) standards in an unshielded
environment. Refer to AN-1109 for PCB-related EMI mitigation
techniques, including board layout and stack-up issues.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition may
differ from the propagation delay time for a low-to-high
transition.
INPUT (VIx)
50%
tPLH
tPHL
OUTPUT (VOx)
50%
Figure 13. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Data Sheet
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM7240/ADuM7241 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM7240/
ADuM7241 components operating under the same conditions.
DC CORRECTNESS
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than approximately 5 μs,
the input side is assumed to be unpowered or nonfunctional,
and the isolator output is forced to a default high state by the
watchdog timer circuit.
MAGNETIC FIELD IMMUNITY
The magnetic field immunity of the ADuM7240/ADuM7241 is
determined by the changing magnetic field, which induces a
voltage in the transformer’s receiving coil large enough to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
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condition of the ADuM7240/ADuM7241 is examined because
it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑ π rn2; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM7240/
ADuM7241 and an imposed requirement that the induced
voltage be, at most, 50% of the 0.5 V margin at the decoder, a
maximum allowable magnetic field at a given frequency can be
calculated. The result is shown in Figure 14.
Rev. 0 | Page 12 of 16
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