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Teilenummer | A025CN02-V0 |
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Beschreibung | Display Module | |
Hersteller | AUO | |
Logo | ||
Gesamt 27 Seiten Doc. version : 0.1
Total pages : 25
Date
: 2004.05.04
Product Specification
2.45〞 COLOR TFT-LCD MODULE
MODEL NAME: A025CN02 V0
www.DataSheet.co.kr
<◆ >Preliminary Specification
< > Final Specification
Note: The content of this
specification is subject to
change.
© 2004 AU Optronics
All Rights Reserved.
DO NOT COPY
Datasheet pdf - http://
Version :
Page :
0
5/26
B. Electrical specifications
1.Pin assignment
a. TFT-LCD panel driving section
Pin no Symbol I/O
1
VSCL2
I VCAC level Selection
Description
2
VSCL1
I VCAC level Selection
3
VSCL0
I VCAC level Selection
4
GND
P Digital ground for gate
5
VCC
PI Digital Power for gate (+3.3V)
Remark
Note 6
Note 6
Note 6
6 VCAC PS VCOM level supply
7 VGoff_H PS Negative power supply (High) for gate
8 VCOM SO Frame polarity output for panel VCOM
9 VGoff_L PS Negative power supply (Low) for gate
10
C3M
C Power setting capacitor connect pin
11 C3P C Power setting capacitor connect pin
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12
VGH
PI Positive power supply for gate (+15V)
13
GND
- Ground
Option
Note 7
14
FB_G
FI Main boost regulator feedback input. FB threshold is 0.6V
15
GND
- Ground
16 DRV_G O Power transistor gate signal for the boost converter
17 GLED1
LED module 1 Cathode
18
VLED1
PI LED module 1 Anode
Option
Note 7
19 N/C
20 N/C
21 DRV_S O Power transistor gate signal for the boost converter
22
FB_S
FI Main boost regulator feedback input. FB threshold is 0.6V
23
GND
P Digital ground for source
24 SHL I Selects left or right shift (Default=”H”)
25
STB
I Standby mode (Normal operation=”H”, Default setting)
Note 1
Note 2
26
VCC
PI Digital power supply for source (+3.3V)
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR
TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM UNIPAC OPTOELECTRONICS CORP.
Datasheetpdf-htp:/www.DataSheet4U.net/
6 Page Version :
Page :
Display period
TVd
14.83
ms
Pulse width
TVp
1
3
DCLK
TH
Vsync setup time
Tvst 12
ns
Vsync hold time
Tvhd
12
ns
DCLK-DATA
timing
Tds
12
-
- ns
DATA
D00~D07
DATA-CLK
timing
Rising time
Falling time
Tdh
Tdrf
-
-
- 10 ns
- 10 ns
Note 1 DCLK Tr and Tf is defined at 10%~90%. Refer to figure as below:
0
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Note 2: Display position
A.. Horizontal display position
The display starts from the data of (105DCLK, THe=105DCLK) as shown in Fig 5.
www.DataSheet.co.kr
( THe : From Hsync falling edge to 1st displayed data.)
B. Vertical display position
Parameter
Symbol
Vertical display position TVS
Min.
Typ.
18
Max.
Unit
TH
Remark
NTSC
b. Timing diagram
Please refer to the attached drawing, from Fig.5 to Fig.8.
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR
TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM UNIPAC OPTOELECTRONICS CORP.
Datasheet pdf - http://www.DataSheet4U.net/
12 Page | ||
Seiten | Gesamt 27 Seiten | |
PDF Download | [ A025CN02-V0 Schematic.PDF ] |
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