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GS8170DW72AC-350 Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8170DW72AC-350
Beschreibung (GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8170DW72AC-350 Datasheet, Funktion
GS8170DW36/72AC-350/333/300/250
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb Σ1x1Dp CMOS I/O
Double Late Write SigmaRAM™
250 MHz–350 MHz
1.8 V VDD
1.8 V I/O
Features
• Double Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
• Pb-Free 209-bump BGA package available
SigmaRAM Family Overview
GS8170DW36/72A SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
ΣRAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The ΣRAMfamily standard
allows a user to implement the interface protocol best suited to
the task at hand.
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
www.DataSheet.co.kr
Functional Description
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Parameter Synopsis
Key Fast Bin Specs
Cycle Time
Access Time
Symbol
tKHKH
tKHQV
- 350
2.86 ns
1.7 ns
Rev: 1.04 4/2005
1/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
Datasheet pdf - http://www.DataSheet4U.net/






GS8170DW72AC-350 Datasheet, Funktion
GS8170DW36/72AC-350/333/300/250
Double Late Write
Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement
Pipeline mode NBT SRAMs.
SigmaRAM Double Late Write with Pipelined Read
Read
W rite
Read
W rite
Read
CK
Address
A
B
C
D
E
F
ADV
/E1
/W
DQ QA DB QC DD
CQ
Hi-Z
Key
www.DataSheet.co.kr
Access
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.
Example of x36 Byte Write Truth Table
Function
Read
Write Byte A
Write Byte B
Write Byte C
Write Byte D
Write all Bytes
Write Abort
W Ba Bb Bc Bd
HX X X X
LL H H H
LH L H H
LH H L H
LH H H L
LL L L L
LH H H H
Rev: 1.04 4/2005
6/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









GS8170DW72AC-350 pdf, datenblatt
.
CK
Address
ADV
/E1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
CQ
Bank 1
Read
A
GS8170DW36/72AC-350/333/300/250
Pipelined Read Bank Switch with E1 Deselect
No Op
Read
Read
Read
XX C D E F
QA
CQ1 + CQ2
CQ
Bank 2
www.DataSheet.co.kr
DQ
Bank 2
QC
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
QD
CMOS Output Driver Impedance Control
CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between
SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point
applications.
Rev: 1.04 4/2005
12/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
Datasheet pdf - http://www.DataSheet4U.net/

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