Datenblatt-pdf.com


GS8170DD18C-330 Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8170DD18C-330
Beschreibung SigmaRAM SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8170DD18C-330 Datasheet, Funktion
209-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
GS8170DD18/36C-333/300/250
18Mb Σ1x2Lp Double Data Rate
SigmaRAM™ SRAM
250 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Double Data Rate Read and Write mode
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V I/O supply
• Pipelined read operation
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 user-programmable chip enable inputs for easy depth
expansion
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
Pipeline mode
tKHKH
tKHQV
- 333
3.0 ns
1.6 ns
SigmaRAM Family Overview
GS8170DD18/36 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. These are the first in
a family of wide, very low voltage CMOS I/O SRAMs
designed to operate at the speeds needed to implement
economical high performance networking systems.
GSI's ΣRAMs are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT, Late Write, or Double Data Rate (DDR) SRAMs. The
logical differences between the protocols employed by these
RAMs hinge mainly on various combinations of address
bursting, output data registering and write cueing. The
ΣRAMfamily standard allows a user to implement the
interface protocol best suited to the task at hand.
Functional Description
Because SigmaRAMs are synchronous devices, address and
read/write control inputs are captured on the rising edge of the
input clock. Write cycles are internally self-timed and initiated
by the rising edge of the clock input. This feature eliminates
complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
DDR mode the device captures Data In on both rising and
falling edges of clock and drives data on both clock edges as
well.www.DataSheet.co.kr
Because the DDR ΣRAM always transfers data in two halves,
A0 is internally set to 0 for the first half of each read or write
transfer, and automatically incremented to 1 for the falling
edge transfer. The address field of a DDR ΣRAM is always one
address pin less than the advertised index depth (e.g., the 1M x
18 has a 512k addressable index).
In Pipeline mode, Single Data Rate (SDR) ΣRAMs incorporate
a rising-edge-triggered output register. In DDR mode, rising-
and falling-edge-triggered output registers are employed. For
read cycles, a DDR SRAM’s output data is staged at the input
of an edge-triggered output register during the access cycle and
then released to the output drivers at the next rising and
subsequent falling edge of clock.
GS817x18/36/72B ΣRAMs are implemented with GSI's high
performance CMOS technology and are packaged in a 209-
bump BGA.
Rev: 1.00e 6/2002
1/31
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/






GS8170DD18C-330 Datasheet, Funktion
Preliminary
GS8170DD18/36C-333/300/250
Background
The central characteristics of ΣRAMs are that they are extremely fast and consume very little power. Because both operating and
interface power is low, ΣRAMs can be implemented in a wide (x36) configuration, providing very high single package bandwidth
(in excess of 20 Gb/s in ordinary pipelined configuration) and very low random access latency (5 ns). The use of very low voltage
circuits in the core and 1.8 V or 1.5 V interface voltages allow the speed, power and density performance of ΣRAMs.
The ΣRAM family of pinouts has been designed to support a number of different common read and write protocols. The following
timing diagrams provide a quick comparison between the late write read and write protocol and the DDR protocol options available
in the context of the ΣRAM standard. This particular datasheet covers the Double Data Rate (DDR) ΣRAM.
The character of the applications for fast synchronous SRAMs in networking systems are extremely diverse. ΣRAMs have been
developed to address the broad variety of applications in the networking market in a manner that can be supported with a unified
development and manufacturing infrastructure. ΣRAMs address each of the bus protocol options commonly found in networking
systems. This allows the ΣRAM to find application in radical shrinks and speed-ups of existing networking chip sets that were
designed for use with older SRAMs, like the NBT, Late Write, or Double Data Rate SRAMs, as well as with new chip sets and
ASIC’s that employ the Echo Clocks and realize the full potential of the ΣRAMs.
Mode Selection Truth Table Standard
L6 M6 J6 Name
0 0 0 Σ1x1Ef
0 0 1 Σ1x1Lf
010
0 1 1 Σ1x2Lp
1 0 0 Σ1x1Ep
1 0 1 Σ1x1Dp
1 1 0 Σ1x1Lp
Function
Early Write, Flow through Read
Late Write, Flow through Read
RFU
DDR
Early Write, Pipelined Read
www.DataSheet.co.kr
Double Late Write, Pipelined Read
Late Write, Pipelined Read
Analogous to...
Flow through Burst RAM
Flow through NBT SRAM
Double Data Rate SRAM
Pipelined Burst RAM
Pipelined NBT SRAM
Pipelined Late Write SRAM
In This Data Sheet?
No
No
n/a
Yes
No
No
No
All address and control inputs (with the exception of PE2, PE3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to rising
clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the
Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the
Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Rev: 1.00e 6/2002
6/31
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









GS8170DD18C-330 pdf, datenblatt
Preliminary
GS8170DD18/36C-333/300/250
Echo Clock Control in Two Banks of SigmaRAM Double Data Rate RAMs
Read
Read
Read
Read
Read
CK
Address
A
B
C
D
E
F
ADV
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
CQ
Bank 1
QA0 QA1
QC0 QC1
CQ1 + CQ2
CQ
Bank 2
DQ
Bank 2
www.DataSheet.co.kr
QB0
QB1
QD0
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
QD1
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read
operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle
in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2
would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.
Rev: 1.00e 6/2002
12/31
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/

12 Page





SeitenGesamt 30 Seiten
PDF Download[ GS8170DD18C-330 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
GS8170DD18C-330SigmaRAM SRAMGSI Technology
GSI Technology

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche