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GS8170DD36C Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8170DD36C
Beschreibung Double Data Rate SigmaRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 29 Seiten
GS8170DD36C Datasheet, Funktion
GS8170DD36C-333/300/250/200
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb Σ1x2Lp CMOS I/O
Double Data Rate SigmaRAM™
200 MHz–333 MHz
1.8 V VDD
1.8 V I/O
Features
• Double Data Rate Read and Write mode
• Late Write; Pipelined read operation
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
SigmaRAM Family Overview
GS8170DD36 SigmaRAMs are built in compliance with the
SigmaRAM pinout standard for synchronous SRAMs. They
are 18,874,368-bit (18Mb) SRAMs. This family of wide, very
low voltage CMOS I/O SRAMs is designed to operate at the
speeds needed to implement economical high performance
networking systems.
ΣRAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The ΣRAMfamily standard
allows a user to implement the interface protocol best suited to
the task at hand.
Functional Description
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
DDR mode the device captures Data In on both rising and
falling edges of clock and drives data on both clock edges as
well.
Because the DDR ΣRAM always transfers data in two halves,
A0 is internally set to 0 for the first half of each read or write
transfer, and automatically incremented to 1 for the falling
edge transfer. The address field of a DDR ΣRAM is always
one address pin less than the advertised index depth (e.g., the
512k x 36 has a 512k addressable index).
www.DataSheet.co.kr
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. DDR ΣRAMs incorporate rising-
and falling-edge-triggered output registers. They also utilize a
Dual Cycle Deselect (DCD) output deselect protocol.
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Parameter Synopsis
Key Fast Bin Specs
Cycle Time
Access Time
Symbol
tKHKH
tKHQV
- 333
3.0 ns
1.8 ns
Rev: 2.03 1/2005
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/






GS8170DD36C Datasheet, Funktion
GS8170DD36C-333/300/250/200
Special Functions
Burst Cycles
SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations.
The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter
generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM
by driving the ADV pin low, into Load mode.
CK
External
Address
I nternal
Address
ADV
/E1
/W
DQ
CQ
SigmaRAM DDR Burst Read with Counter Wrap-around
Read
Continue
Continue
Read
Continue
A2 XX XX B0 XX XX
A2 A3 A0 A1 A2 A3 B0 B1 B2 B3 B1
Counter Wraps
www.DataSheet.co.kr
QA2 QA3 QA0 QA1 QA2 QA3 QB0 QB1
Rev: 2.03 1/2005
6/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









GS8170DD36C pdf, datenblatt
GS8170DD36C-333/300/250/200
DDR Late Write, Pipelined Read Truth Table
CK
E1
(tn)
E
(tn)
ADV
(tn)
W
(tn)
Previous
Operation
Current Operation
DQ/CQ DQ/CQ DQ/CQ DQ/CQ
(tn) (tn+½) (tn+1) (tn+1½)
01 X F 0 X
X
Bank Deselect
***/***
Hi-Z/Hi-Z
01 X X 1 X Bank Deselect Bank Deselect (Continue)
Hi-Z/Hi-Z
Hi-Z/Hi-Z
01 1 T 0 X
X
Deselect
***/***
Hi-Z/CQ
01 X X 1 X
Deselect
Deselect (Continue)
Hi-Z/CQ
Hi-Z/CQ
01 0 T 0 0
X
Write
Loads new address
***/***
D1/CQ D2/CQ
01 X X 1 X
Write
Write Continue
Increments address by 2
Dn-2/CQ Dn-1/CQ Dn/CQ Dn+1/CQ
01 0 T 0 1
X
Read
Loads new address
***/***
Q1/CQ Q2/CQ
01 X X 1 X
Read
Read Continue
Increments address by 2
Qn-2/CQ Qn-2/CQ Qn/CQ Qn+1/CQ
Notes:
www.DataSheet.co.kr
1. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
3. “***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
4. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
5. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
6. One (1) Continue operation may be initiated after a Read or Write operation is initiated to burst transfer a total of four (4) distinct pieces of
data per single external address input. If a second (2nd) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
Rev: 2.03 1/2005
12/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/

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