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PDF AD9642 Data sheet ( Hoja de datos )
| Número de pieza | AD9642 | |
| Descripción | 1.8 V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
14-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter (ADC)
AD9642
FEATURES
SNR = 71.0 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 83 dBc at 185 MHz AIN and 250 MSPS
−152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS AIN, 250 MSPS
Total power consumption: 390 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The AD9642 is a 14-bit analog-to-digital converter (ADC) with
sampling speeds of up to 250 MSPS. The AD9642 is designed to
support communications applications, where low cost, small
size, wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty
cycle, allowing the converter to maintain excellent performance.
The ADC output data is routed directly to the external
14-bit LVDS output port.
Flexible power-down options allow significant power savings,
when desired.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
VIN+
VIN–
VCM
PIPELINE 14
14-BIT
ADC
AD9642
PARALLEL
DDR LVDS
AND
DRIVERS
REFERENCE
SERIAL PORT
1-TO-8
CLOCK
DIVIDER
D0±/D1±
D12±/D13±
DCO±
SCLK SDIO
CSB
CLK+ CLK–
Figure 1.
Programming for setup and control is accomplished using a
3-wire SPI-compatible serial interface.
The AD9642 is available in a 32-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
2. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating LVDS outputs.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 350 MHz.
4. 3-pin, 1.8 V SPI port for register programming and readback.
5. Pin compatibility with the AD9634, allowing a simple migra-
tion from 14 bits to 12 bits, and with the AD6672.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9642
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless
otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION
(SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE
(SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Temperature
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
AD9642-170
Min Typ Max
72.5
72.2
70.7
71.8
71.2
70.7
71.5
71.3
69.6
70.8
70.3
69.7
11.6
11.6
11.5
11.4
11.3
−96
−95
−82
−97
−86
−84
96
95
82
97
86
84
−99
−95
−87
−98
−96
−97
AD9642-210
Min Typ Max
72.4
72.2
70.0
71.6
71.5
71.0
71.5
71.3
68.7
70.6
70.5
70.1
11.6
11.6
11.4
11.4
11.3
−96
−92
−79
−94
−95
−84
96
92
79
94
95
84
−98
−97
−81
−96
−97
−94
AD9642-250
Min Typ Max
72.2
72.0
71.8
71.4
68.6
70.9
71.2
71.0
70.9
70.4
67.5
70.0
11.5
11.5
11.5
11.4
11.3
−90
−89
−90
−86
−80
−86
90
89
90
86
80
86
−95
−98
−97
−96
−81
−95
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. B | Page 4 of 28
5 Page 
AD9642
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS,
32k sample, TA = 25°C, unless otherwise noted.
0
170MSPS
90.1MHz @ –1dBFS
–20 SNR = 71.82dB (72.2dBFS)
SFDR = 93dBc
–40
0
170MSPS
305.1MHz @ –1dBFS
–20 SNR = 68.0dB (69.0dBFS)
SFDR = 86dBc
–40
–60
SECOND HARMONIC
–80
–100
THIRD HARMONIC
–60
–80
–100
SECOND HARMONIC
THIRD HARMONIC
–120
–120
–140
0
10 20 30 40 50 60
FREQUENCY (MHz)
70 80
Figure 4. AD9642-170 Single-Tone FFT with fIN = 90.1 MHz
–140
0
10 20
30 40 50 60
FREQUENCY (MHz)
70 80
Figure 7. AD9642-170 Single-Tone FFT with fIN = 305.1 MHz
0
170MSPS
185.1MHz @ –1dBFS
–20 SNR = 70.2dB (71.2dBFS)
SFDR = 86dBc
–40
–60
–80
–100
THIRD HARMONIC
SECOND HARMONIC
–120
–140
0
10 20
30 40 50 60
FREQUENCY (MHz)
70 80
Figure 5. AD9642-170 Single-Tone FFT with fIN = 185.1 MHz
120
SFDR (dBFS)
100
80 SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
20
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
INPUT AMPLITUDE (dBFS)
0
Figure 8. AD9642-170 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 90.1 MHz, fS = 170 MSPS
0
170MSPS
220.1MHz @ –1dBFS
–20 SNR = 69.7dB (70.7dBFS)
SFDR = 84dBc
–40
–60
–80
–100
THIRD HARMONIC
SECOND HARMONIC
–120
–140
0
10 20
30 40 50 60
FREQUENCY (MHz)
70 80
Figure 6. AD9642-170 Single-Tone FFT with fIN = 220.1 MHz
100
95 SFDR (dBc)
90
85
80
SNR (dBFS)
75
70
65
60
60 90 120 150 180 210 240 270 300 330
75 105 135 165 195 225 255 285 315 345
FREQUENCY (MHz)
Figure 9. AD9642-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN),
fS = 170 MSPS
Rev. B | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD9642.PDF ] | |
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