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AD7608 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7608
Beschreibung 8-Channel DAS
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD7608 Datasheet, Funktion
Data Sheet
8-Channel DAS with 18-Bit, Bipolar,
Simultaneous Sampling ADC
AD7608
FEATURES
8 simultaneously sampled inputs
True bipolar analog input ranges: ±10 V, ±5 V
Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE
Fully integrated data acquisition solution
Analog input clamp protection
Input buffer with 1 MΩ analog input impedance
Second-order antialiasing analog filter
On-chip accurate reference and reference buffer
18-bit ADC with 200 kSPS on all channels
Oversampling capability with digital filter
Flexible parallel/serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Pin compatible solutions from 14-bits to 18-bits
Performance
7 kV ESD rating on analog input channels
98 dB SNR, −107 dB THD
Low power: 100 mW
Standby mode: 25 mW
64-lead LQFP package
APPLICATIONS
Power line monitoring and protection systems
Multiphase motor controls
Instrumentation and control systems
Multiaxis positioning systems
Data acquisition systems (DAS)
COMPANION PRODUCTS
External References: ADR421, ADR431
Digital Isolators: ADuM1402, ADuM5000, ADuM5402
Voltage Regulator Design Tool: ADIsimPower, Supervisor
Parametric Search
Complete list of complements on AD7608 product page
Table 1. High Resolution, Bipolar Input, Simultaneous
Sampling DAS Solutions
Single-
Ended
Resolution Inputs
True Number of
Differential Simultaneous
Inputs
Sampling Channels
18 Bits
AD76081 AD7609
8
16 Bits
AD7606
8
AD7606-6
6
AD7606-4
4
www.DataSheet.co.kr
14 Bits
AD7607
8
1 Patent pending.
V1
V1GND
V2
V2GND
V3
V3GND
V4
V4GND
V5
V5GND
V6
V6GND
V7
V7GND
V8
V8GND
CLAMP 1M
CLAMP
1M
CLAMP 1M
CLAMP
1M
CLAMP 1M
CLAMP
1M
CLAMP 1M
CLAMP
1M
CLAMP 1M
CLAMP
1M
CLAMP 1M
CLAMP
1M
CLAMP 1M
CLAMP
1M
CLAMP 1M
CLAMP
1M
FUNCTIONAL BLOCK DIAGRAM
AVCC
AVCC
REGCAP REGCAP REFCAPB REFCAPA
RFB
RFB
SECOND
ORDER LPF
T/H
RFB
RFB
SECOND
ORDER LPF
T/H
RFB
RFB
SECOND
ORDER LPF
T/H
2.5V
LDO
2.5V
LDO
2.5V
REF
RFB
RFB
SECOND
ORDER LPF
T/H
RFB
RFB
SECOND
ORDER LPF
T/H
8:1
MUX
18-BIT
SAR
DIGITAL
FILTER
SERIAL
PARALLEL/
SERIAL
INTERFACE
RFB
RFB
SECOND
ORDER LPF
T/H
RFB
RFB
SECOND
ORDER LPF
T/H
AD7608
CLK OSC
PARALLEL
RFB
RFB
SECOND
ORDER LPF
T/H
CONTROL
INPUTS
AGND
CONVST A CONVST B RESET RANGE
Figure 1.
REFIN/REFOUT
REF SELECT
AGND
OS 2
OS 1
OS 0
DOUTA
DOUTB
RD/SCLK
CS
PAR/SER SEL
VDRIVE
DB[15:0]
BUSY
FRSTDATA
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/






AD7608 Datasheet, Funktion
AD7608
Data Sheet
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
tCYCLE
tCONV
tWAKE-UP STANDBY
tWAKE-UP SHUTDOWN
Internal Reference
External Reference
tRESET
tOS_SETUP
tOS_HOLD
t1
t2
t3
t4
t5 210F9F
t6
t7
PARALLEL/BYTE READ
OPERATION
t8
t9
t10
t11
t12
Limit at TMIN, TMAX
Min Typ Max
5
3.45
7.87
16.05
33
66
133
257
4
5
10.5
4.15
9.1
18.8
39
78
158
315
100
30
13
50
20
20
40
25
25
0
0.5
25
25
0
0
16
21
25
32
15
22
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
1/throughput rate
Parallel mode, reading during or after conversion; or serial mode: VDRIVE =
3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines
Serial mode reading during conversion; VDRIVE = 2.7 V
Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines
Conversion time
Oversampling off
Oversampling by 2
Oversampling by 4
Oversampling by 8
Oversampling by 16
Oversampling by 32
Oversampling by 64
STBYE rising edge to CONVST x rising edge; power-up time from
A
standby mode
STBYE rising edge to CONVST x rising edge; power-up time from
AA
shutdown mode
STBYE rising edge to CONVST x rising edge; power-up time from
AA
shutdown mode
RESET high pulse widthwww.DataSheet.co.kr
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CSE falling edge setup time
AA
Maximum delay allowed between CONVST A, CONVST B rising edges
Maximum time between last CSE rising edge and BUSY falling edge
AA
Minimum delay between RESET low to CONVST x high
CSE to RDE setup time
AA
AA
CSE to RDE hold time
AA
AA
RDE low pulse width
AA
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
RDE high pulse width
AA
CSE high pulse width (see Figure 5); CSE and RDE linked
AA
AA
AA
Rev. A | Page 6 of 32
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









AD7608 pdf, datenblatt
AD7608
Data Sheet
Pin No.
11
12
13
14
15
22 to 16
23
24
25
31 to 27
32
33
Type 1
12F1F
DI
Mnemonic
RESET
DI RDE/SCLK
AA
DI CSE
A
DO BUSY
DO FRSTDATA
DO DB[6:0]
P VDRIVE
DO DB7/DOUTA
DO DB8/DOUTB
DO DB[13:9]
DO/DI DB14
DO/DI DB15
Description
Reset Input. When set to logic high, the rising edge of RESET resets the AD7608. Once tWAKE-UP has
elapsed, the part should receive a RESET pulse after power up. The RESET high pulse should be
typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If
a RESET pulse is applied during a read, the contents of the output registers resets to all zeros.
Parallel Data Read Control Input when Parallel Interface is Selected (RDE)/Serial Clock Input when the
AA
Serial Interface is Selected (SCLK). When both CSE and RDE are logic low in parallel mode, the output
AA
AA
bus is enabled.
In parallel mode, two RDE pulses are required to read the full 18 bits of conversion results from each
AA
channel. The first RDE pulse outputs DB[17:2], the second RDE pulse outputs DB[1:0].
AA
AA
In serial mode, this pin acts as the serial clock input for data transfers. The CSE falling edge takes the
AA
data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion
result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data
outputs. For further information, see the Conversion Control section.
Chip Select. This active low logic input frames the data transfer. When both CSE and RDE are logic low
AA
AA
in parallel mode, the output bus, DB[15:0], is enabled and the conversion result is output on the
parallel data bus lines. In serial mode, the CSE is used to frame the serial read transfer and clock out
AA
the MSB of the serial output data.
Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges
and indicates that the conversion process has started. The BUSY output remains high until the
conversion process for all channels is complete. The falling edge of BUSY signals that the conversion
data is being latched into the output data registers and is available to be read after a Time t4. Any
data read while BUSY is high must be complete before the falling edge of BUSY occurs. Rising edges
on CONVST A or CONVST B have no effect while the BUSY signal is high.
Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back
on either the parallel or serial interface. When the CSE input is high, the FRSTDATA output pin is in
AA
three-state. The falling edge of CSE takes FRSTDATA out of three-state. In parallel mode, the falling
AA
edge of RDE corresponding to the result of V1 then sets the FRSTDATA pin high indicating that the
AA
result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low
following the third falling edge of RDE. In serial mode, FRSTDATA goes high on the falling edge of CSE
AA
AA
as
this
clocks
out
the
MSB
of
V1
on
DOUTA.www.DataSheet.co.kr
It
returns
low
on
the
18th
SCLK
falling
edge
after
the
CSE
AA
falling edge. See the Conversion Control section for more details.
Parallel Output Data Bits, DB6 to DB0. When PARE/SER SEL = 0, these pins act as three-state parallel
AA
digital output pins. When CSE and RDE are low, these pins are used to output DB8 to DB2 of the
AA
AA
conversion result during the first RDE pulse and output 0 during the second RDE pulse. When PARE/SER
AA
AA
AA
SEL = 1, these pins should be tied to GND.
Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the
operating voltage of the interface. This pin is nominally at the same supply as the supply of the host
interface (that is, DSP and FPGA).
Parallel
Output
Data
Bit
7
(DB7)/Serial
Inter
face
Data
Output
Pin
(DOUTA).
When
PARE/SER
AA
SEL
=
0,
this
pin acts as a three-state parallel digital output pin. When CSE and RDE are low, this pin is used to
AA
AA
output
DB9
of
the
conversion
result.
When
PARE/SER
AA
SEL
=
1,
this
pin
functions
as
DOUTA
and
outputs
serial conversion data. See the Conversion Control section for further details.
Parallel
Output
Data
Bit
8
(DB8)/Serial
Inter
face
Data
Output
Pin
(DOUTB).
When
PARE/SER
AA
SEL
=
0,
this
pin acts as a three-state parallel digital output pin. When CSE and RDE are low, this pin is used to
AA
AA
output
DB10
of
the
conversion
result.
When
PARE/SER
AA
SEL
=
1,
this
pin
functions
as
DOUTB
and
outputs serial conversion data. See the Conversion Control section for further details.
Parallel Output Data Bits, DB13 to DB9. When PARE/SER SEL = 0, these pins act as three-state parallel
AA
digital output pins. When CSE and RDE are low, these pins are used to output DB15 to DB11 of the
AA
AA
conversion result during the first RDE pulse and output zero during the second RDE pulse. When
AA
AA
PARE/SER SEL = 1, these pins should be tied to GND.
AA
Parallel Output Data Bit 14 (DB14). When PARE/SER SEL = 0, this pin act as three-state parallel digital
AA
output pin. When CSE and RDE are low, this pin is used to output DB16 of the conversion result during the
AA
AA
first RDE pulse and DB0 of the same conversion result during the second RDE pulse. When PARE/SER
AA
AA
AA
SEL = 1, this pins should be tied to GND.
Parallel Output Data Bit 15 (DB15). When PARE/SER SEL = 0, this pin acts as three-state parallel digital
AA
output pin. This pin is used to output DB17 of the conversion result during the first RDE pulse and
AA
DB1 of the same conversion result during the second RDE pulse. When PARE/SER SEL = 1, this pins
AA
AA
should be tied to GND.
Rev. A | Page 12 of 32
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12 Page





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