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W681360 Schematic ( PDF Datasheet ) - Nuvoton Technology

Teilenummer W681360
Beschreibung 3V SINGLE-CHANNEL 13-BIT LINEAR VOICE-BAND CODEC
Hersteller Nuvoton Technology
Logo Nuvoton Technology Logo 




Gesamt 34 Seiten
W681360 Datasheet, Funktion
W681360
3V SINGLE-CHANNEL
13-BIT LINEAR
VOICE-BAND CODEC
www.DataSheet.co.kr
Data Sheet
Revision A.5
-1-
Datasheet pdf - http://www.DataSheet4U.net/






W681360 Datasheet, Funktion
W681360
5. PIN CONFIGURATION
VREF
RO-
PAI
PAO-
PAO+
VD D
FSR
PCMR
BCLKR
P UI
1 20
2 19
3 18
4 17
5 W681360 16
SINGLE
6 15
CHANNEL
7 CODEC 14
8 13
9 12
10 11
SOG, SSOP,TSSOP
www.DataSheet.co.kr
VA G
AI+
AI-
AO
HB
VSS
FST
PCMT
BCLKT
MCLK
32 31 30 29 28 27 26
RO- 1
25 NC
PAI 2
PAO- 3
24 AI-
23 AO
NC 4
22 HB
PAO+ 5
VDD 6
FSR 7
PCMR 8
BCLKR 9
21 NC
20 VSS
19 FST
18 NC
17 PCMT
10 11 12 13 14 15 16
QFN-32L
Publication Release Date: January 2011
- 6 - Revision A.5
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









W681360 pdf, datenblatt
W681360
7.2.1. Receive Gain Adjust Mode
The W681360 can be put in the receive path adjust mode by applying a logic “1” to the BCLKR pin
while all other clocks are clocked normally. The device is then in a position to read 16-bits of data,
with three additional coefficient bits an addend to the 13-bit digital voice data. These three coefficients
are used to program a receive path attenuation, thereby allowing the receive signal to be attenuated
according to the values in the following table. If the feature is not used the default value is 0dB.
Coefficient
000
001
010
011
100
101
110
111
Attenuation (dB)
0
3
6
9
12
15
18
21
TABLE 7.2: ATTENUATION COEFFICIENT RELATIONSHIP IN RECEIVE GAIN ADJUST MODE
www.DataSheet.co.kr
7.3. POWER MANAGEMENT
7.3.1. Analog and Digital Supply
The power supply for the analog and digital parts of the W681360 must be 2.7V to 5.25V. This supply
voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 F
ceramic capacitor.
7.3.2. Analog Ground Reference Bypass
The system has an internal precision voltage reference which generates the VDD/2 mid-supply analog
ground voltage. This voltage needs to be decoupled to VSS at the VREF pin through a 0.1 F ceramic
capacitor.
7.3.3. Analog Ground Reference Voltage Output
The analog ground reference voltage is available for external reference at the VAG pin. This voltage
needs to be decoupled to VSS through a 0.01 F ceramic capacitor. The analog ground reference
voltage is generated from the voltage on the VREF pin and is also used for the internal signal
processing.
Publication Release Date: January 2011
- 12 -
Revision A.5
Datasheet pdf - http://www.DataSheet4U.net/

12 Page





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