C8051F824 Datasheet PDF - Silicon Laboratories
| Part Number | C8051F824 | |
| Description | (C8051F80x - C8051F83x) Mixed Signal ISP Flash MCU Family | |
| Manufacturers | Silicon Laboratories | |
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www.DataSheet.co.kr
Capacitance to Digital Converter
- Supports buttons, sliders, wheels, and capacitive
proximity sensing
- Fast 40 µs per channel conversion time
- 16-bit resolution
- Up to 16 input channels
- Auto-scan and wake-on-touch
- Auto-accumulate 4x, 8x, 16, 32x, and 64x samples
Analog Peripherals
- 10-Bit ADC
• Up to 500 ksps
• Up to 16 external single-ended inputs
• VREF from on-chip VREF, external pin or VDD
• Internal or external start of conversion source
• Built-in temperature sensor
- Comparator
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
C8051F80x-83x
Mixed Signal ISP Flash MCU Family
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- Up to 512 bytes internal data RAM (256 + 256)
- Up to 16 kB Flash; In-system programmable in
512-byte sectors
Digital Peripherals
- 17 or 13 Port I/O with high sink current
- Hardware enhanced UART, SMBus™ (I2C compati-
ble), and enhanced SPI™ serial ports
- Three general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with 3
capture/compare modules and enhanced PWM
functionality
- Real time clock mode using timer and crystal
Clock Sources
- 24.5 MHz ±2% Oscillator
• Supports crystal-less UART operation
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly; useful
in power saving modes
Supply Voltage 1.8 to 3.6 V
- Built-in voltage supply monitor
24-Pin QSOP, 20-Pin QFN, 16-Pin SOIC
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A
M
U
10-bit TEMP
500 ksps SENSOR
X ADC
+
Capacitive
Sense
–
VOLTAGE
COMPARATOR
DIGITAL I/O
UART
Port 0
SMBus
SPI
PCA
Timer 0
Timer 1
P1.0-
P1.3
P1.4-
P1.7
Timer 2
P2.0
24.5 MHz PRECISION INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
512 B RAM
POR WDT
Rev. 1.0 7/10
Copyright © 2010 by Silicon Laboratories
C8051F80x-83x
Datasheet pdf - http://www.DataSheet4U.net/
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www.DataSheet.co.kr
C8051F80x-83x
23.1. Port I/O Modes of Operation.......................................................................... 139
23.1.1. Port Pins Configured for Analog I/O...................................................... 139
23.1.2. Port Pins Configured For Digital I/O...................................................... 139
23.1.3. Interfacing Port I/O to 5 V Logic ............................................................ 140
23.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 140
23.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 140
23.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 141
23.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 142
23.3. Priority Crossbar Decoder ............................................................................. 143
23.4. Port I/O Initialization ...................................................................................... 147
23.5. Port Match ..................................................................................................... 150
23.6. Special Function Registers for Accessing and Configuring Port I/O ............. 152
24. Cyclic Redundancy Check Unit (CRC0)............................................................. 159
24.1. 16-bit CRC Algorithm..................................................................................... 160
24.2. 32-bit CRC Algorithm..................................................................................... 161
24.3. Preparing for a CRC Calculation ................................................................... 162
24.4. Performing a CRC Calculation ...................................................................... 162
24.5. Accessing the CRC0 Result .......................................................................... 162
24.6. CRC0 Bit Reverse Feature............................................................................ 166
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 167
25.1. Signal Descriptions........................................................................................ 168
25.1.1. Master Out, Slave In (MOSI)................................................................. 168
25.1.2. Master In, Slave Out (MISO)................................................................. 168
25.1.3. Serial Clock (SCK) ................................................................................ 168
25.1.4. Slave Select (NSS) ............................................................................... 168
25.2. SPI0 Master Mode Operation ........................................................................ 168
25.3. SPI0 Slave Mode Operation .......................................................................... 170
25.4. SPI0 Interrupt Sources .................................................................................. 171
25.5. Serial Clock Phase and Polarity .................................................................... 171
25.6. SPI Special Function Registers ..................................................................... 173
26. SMBus................................................................................................................... 180
26.1. Supporting Documents .................................................................................. 181
26.2. SMBus Configuration..................................................................................... 181
26.3. SMBus Operation .......................................................................................... 181
26.3.1. Transmitter Vs. Receiver....................................................................... 182
26.3.2. Arbitration.............................................................................................. 182
26.3.3. Clock Low Extension............................................................................. 182
26.3.4. SCL Low Timeout.................................................................................. 182
26.3.5. SCL High (SMBus Free) Timeout ......................................................... 183
26.4. Using the SMBus........................................................................................... 183
26.4.1. SMBus Configuration Register.............................................................. 183
26.4.2. SMB0CN Control Register .................................................................... 187
26.4.2.1. Software ACK Generation ............................................................ 187
26.4.2.2. Hardware ACK Generation ........................................................... 187
26.4.3. Hardware Slave Address Recognition .................................................. 189
Rev. 1.0
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for C8051F824 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ C8051F824.PDF Datasheet ] | |
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