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W9825G6DH Schematic ( PDF Datasheet ) - Winbond

Teilenummer W9825G6DH
Beschreibung 4M X 4 BANKS X 16 BITS SDRAM
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W9825G6DH Datasheet, Funktion
www.DataSheet.co.kr
W9825G6DH
4M × 4 BANKS × 16 BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. AVAILABLE PART NUMBER...................................................................................................... 4
4. PIN CONFIGURATION ............................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION.................................................................................................... 7
7.1 Power Up and Initialization ............................................................................................. 7
7.2 Programming Mode Register.......................................................................................... 7
7.3 Bank Activate Command ................................................................................................ 7
7.4 Read and Write Access Modes ...................................................................................... 7
7.5 Burst Read Command .................................................................................................... 8
7.6 Burst Write Command .................................................................................................... 8
7.7 Read Interrupted by a Read ........................................................................................... 8
7.8 Read Interrupted by a Write............................................................................................ 8
7.9 Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 8
7.12 Addressing Sequence of Sequential Mode .................................................................... 9
7.13 Addressing Sequence of Interleave Mode...................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode ....................................................................................................... 11
7.18 No Operation Command............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
8. OPERATION MODE ................................................................................................................. 12
9. ELECTRICAL CHARACTERISTICS......................................................................................... 13
9.1 Absolute Maximum Ratings .......................................................................................... 13
9.2 Recommended DC Operating Conditions .................................................................... 13
Publication Release Date: Aug. 13, 2007
- 1 - Revision A10
Datasheet pdf - http://www.DataSheet4U.net/






W9825G6DH Datasheet, Funktion
www.DataSheet.co.kr
6. BLOCK DIAGRAM
W9825G6DH
CLK
CKE
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIG NAL
G E N E R ATO R
A10
A0
A9
A11
A12
BS0
BS1
ADDRESS
BUFFER
MODE
REG IST ER
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
DATA CONTROL
C IR C U IT
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DQ
BUFFER
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
DQ0
DQ15
LDQM
UDQM
Note: The cell array configuration is 8192 * 512 * 16.
-6-
Publication Release Date: Aug. 13, 2007
Revision A10
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









W9825G6DH pdf, datenblatt
www.DataSheet.co.kr
W9825G6DH
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1) , (2))
COMMAND
Bank Active
Bank Precharge
Precharge All
Write
Write with Auto-
precharge
Read
Read with Auto-
precharge
Mode Register Set
No-operation
Burst Stop
Device Deselect
Auto-refresh
Self-refresh Entry
Self-refresh Exit
Clock Suspend Mode
Entry
Power Down Mode
Entry
Clock Suspend Mode
Exit
Power Down Mode
Exit
Data Write/Output
Enable
Data Write/Output
Disable
DEICE
STATE
Idle
Any
Any
Active (3)
CKEn-1 CKEn
Hx
Hx
Hx
Hx
Active (3)
H
x
Active (3)
H
x
Active (3)
H
x
Idle
Any
Active (4)
Any
Idle
Idle
Idle
(S.R.)
H
H
H
H
H
H
L
L
x
x
x
x
H
L
H
H
Active H L
Idle
Active (5)
H
H
L
L
Active L H
Any
(Power Down)
L
L
H
H
Active H x
Active H x
DQM
x
x
x
x
BS0, 1
v
v
x
v
A10
A0A9
A11, A12
vv
Lx
Hx
Lv
CS
L
L
L
L
x vH v L
x vL v L
x vH v L
x vv v L
x xx x L
x xx x L
x xx x H
x xx x L
x xx x L
x xx x H
x xx x L
x xx x x
x xx x H
x xx x L
x xx x x
x xx x H
x xx x L
L xx x x
H xx x x
Notes:
(1) v = valid x = Don't care L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
RAS
L
L
L
H
H
H
H
L
H
H
x
L
L
x
H
x
x
H
x
x
H
x
x
CAS WE
HH
HL
HL
LL
LL
LH
LH
LL
HH
HL
xx
LH
LH
xx
Hx
xx
xx
Hx
xx
xx
Hx
xx
xx
- 12 -
Publication Release Date: Aug. 13, 2007
Revision A10
Datasheet pdf - http://www.DataSheet4U.net/

12 Page





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