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W9812G2IB Schematic ( PDF Datasheet ) - Winbond

Teilenummer W9812G2IB
Beschreibung 1M x 4 BANKS x 32BITS SDRAM
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W9812G2IB Datasheet, Funktion
www.DataSheet.co.kr
W9812G2IB
1M × 4 BANKS × 32BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION .............................................................................................................. 3
2. FEATURES...................................................................................................................................... 3
3. AVAILABLE PART NUMBER .......................................................................................................... 3
4. BALL CONFIGURATION................................................................................................................. 4
5. BALL DESCRIPTION ...................................................................................................................... 5
6. BLOCK DIAGRAM........................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION ........................................................................................................ 7
7.1 Power Up and Initialization ................................................................................................. 7
7.2 Programming Mode Register .............................................................................................. 7
7.3 Bank Activate Command .................................................................................................... 7
7.4 Read and Write Access Modes .......................................................................................... 7
7.5 Burst Read Command ........................................................................................................ 8
7.6 Burst Write Command......................................................................................................... 8
7.7 Read Interrupted by a Read ............................................................................................... 8
7.8 Read Interrupted by a Write................................................................................................ 8
7.9 Write Interrupted by a Write ................................................................................................ 8
7.10 Write Interrupted by a Read................................................................................................ 8
7.11 Burst Stop Command.......................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode......................................................................... 9
7.13 Addressing Sequence of Interleave Mode.......................................................................... 9
7.14 Auto-precharge Command................................................................................................ 10
7.15 Precharge Command........................................................................................................ 10
7.16 Self Refresh Command..................................................................................................... 10
7.17 Power Down Mode............................................................................................................ 11
7.18 No Operation Command ................................................................................................... 11
7.19 Deselect Command .......................................................................................................... 11
7.20 Clock Suspend Mode........................................................................................................ 11
8. OPERATION MODE...................................................................................................................... 12
8.1 Simplified Stated Diagram ................................................................................................ 13
9. ELECTRICAL CHARACTERISTICS ............................................................................................. 14
9.1 Absolute Maximum Ratings .............................................................................................. 14
9.2 Recommended DC Operating Conditions ........................................................................ 14
9.3 Capacitance ...................................................................................................................... 15
Publication Release Date: Mar. 09, 2010
- 1 - Revision A04
Datasheet pdf - http://www.DataSheet4U.net/






W9812G2IB Datasheet, Funktion
www.DataSheet.co.kr
6. BLOCK DIAGRAM
W9812G2IB
CLK
CKE
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
MODE
REGISTER
A0 AND
ADDRESS
EMRS
BUFFER
A9
A11
BS0
BS1
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
DATA
CONTROL
CIRCUIT
.
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DMn
DQ
BUFFER
DQ0
DQ31
DQMn
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE: The cell array configuration is 4096 * 256 * 32
-6-
Publication Release Date: Mar. 09, 2010
Revision A04
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









W9812G2IB pdf, datenblatt
www.DataSheet.co.kr
W9812G2IB
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1), (2))
COMMAND
DEVICE
STATE
CKEn-1 CKEn DQM BS0, 1
A10
A0A9
A11
CS
Bank Active
Idle
Bank Precharge
Any
Precharge All
Any
Write
Active (3)
Write with Auto-precharge
Active (3)
Read
Active (3)
Read with Auto-precharge Active (3)
Mode Register Set
Idle
No – Operation
Any
Burst Stop
Active (4)
Device Deselect
Any
Auto - Refresh
Idle
Self - Refresh Entry
Idle
Self Refresh Exit
Clock suspend Mode Entry
idle
(S.R.)
Active
Power Down Mode Entry
Idle Active (5)
Clock Suspend Mode Exit
Power Down Mode Exit
Active
Any
(power down)
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
L
L
x x v v vL
x x v L xL
x x xH xL
x x v L vL
x x vH vL
x x v L vL
x x vH vL
x x v v vL
x x x x xL
x x x x xL
x x x x xH
H x x x xL
L x x x xL
H x x x xH
H x x x xL
L x x x xx
L x x x xH
L x x x xL
H x x x xx
H x x x xH
H x x x xL
RAS CAS WE
L HH
LHL
LHL
HL L
HL L
HLH
HLH
LLL
HHH
HH L
xxx
L LH
L LH
xxx
HH x
xxx
xxx
HH x
xxx
xxx
HH x
Data write/Output Enable
Active
H
x L x x x xxxx
Data Write/Output Disable
Active
H
x H x x x xxxx
Notes:
(1) v = valid x = Don’t care L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
- 12 -
Publication Release Date: Mar. 09, 2010
Revision A04
Datasheet pdf - http://www.DataSheet4U.net/

12 Page





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