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W9464G6JH Schematic ( PDF Datasheet ) - Winbond

Teilenummer W9464G6JH
Beschreibung 1M X 4 BANKS X 16 BITS DDR SDRAM
Hersteller Winbond
Logo Winbond Logo 




Gesamt 52 Seiten
W9464G6JH Datasheet, Funktion
www.DataSheet.co.kr
W9464G6JH
1M 4 BANKS 16 BITS DDR SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 4
2. FEATURES ................................................................................................................................. 4
3. KEY PARAMETERS ................................................................................................................... 5
4. PIN CONFIGURATION ............................................................................................................... 6
5. PIN DESCRIPTION..................................................................................................................... 7
6. BLOCK DIAGRAM ...................................................................................................................... 8
7. FUNCTIONAL DESCRIPTION.................................................................................................... 9
7.1 Power Up Sequence....................................................................................................... 9
7.2 Command Function ...................................................................................................... 10
7.2.1
Bank Activate Command ........................................................................... 10
7.2.2
Bank Precharge Command........................................................................ 10
7.2.3
Precharge All Command............................................................................ 10
7.2.4
Write Command ......................................................................................... 10
7.2.5
Write with Auto-precharge Command........................................................ 10
7.2.6
Read Command ......................................................................................... 10
7.2.7
Read with Auto-precharge Command ....................................................... 10
7.2.8
Mode Register Set Command.................................................................... 11
7.2.9
Extended Mode Register Set Command ................................................... 11
7.2.10 No-Operation Command............................................................................ 11
7.2.11 Burst Read Stop Command ....................................................................... 11
7.2.12 Device Deselect Command ....................................................................... 11
7.2.13 Auto Refresh Command ............................................................................ 11
7.2.14 Self Refresh Entry Command .................................................................... 12
7.2.15 Self Refresh Exit Command....................................................................... 12
7.2.16 Data Write Enable /Disable Command ...................................................... 12
7.3 Read Operation............................................................................................................. 12
7.4 Write Operation............................................................................................................. 13
7.5 Precharge ..................................................................................................................... 13
7.6 Burst Termination.......................................................................................................... 13
7.7 Refresh Operation......................................................................................................... 13
7.8 Power Down Mode ....................................................................................................... 14
7.9 Input Clock Frequency Change during Precharge Power Down Mode........................ 14
7.10 Mode Register Operation.............................................................................................. 14
Publication Release Date: Oct. 20, 2011
- 1 - Revision A02
Datasheet pdf - http://www.DataSheet4U.net/






W9464G6JH Datasheet, Funktion
www.DataSheet.co.kr
4. PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
W9464G6JH
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 CLK
45 CLK
44 CKE
43 NC
42 NC
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
-6-
Publication Release Date: Oct. 20, 2011
Revision A02
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









W9464G6JH pdf, datenblatt
www.DataSheet.co.kr
W9464G6JH
REFRESH cycles at an average periodic interval of tREFI (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be
posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO
REFRESH command and the next AUTO REFRESH command is 8 * tREFI.
7.2.14 Self Refresh Entry Command
( RAS = “L”, CAS = “L”, WE = “H”, CKE = “L”, BA0, BA1, A0 to A11 = Don’t Care)
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of
the system is powered down. When in the self refresh mode, the DDR SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF
REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is
enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command
can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is
an SSTL_2 input, VREF must be maintained during SELF REFRESH.
7.2.15 Self Refresh Exit Command
(CKE = “H”, CS = “H” or CKE = “H”, RAS = “H”, CAS = “H”)
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be
stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP
commands issued for tXSNR because time is required for the completion of any internal refresh in
progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for
200 clock cycles before applying any other command.
The use of SELF REFREH mode introduces the possibility that an internally timed event can be
missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an
extra auto refresh command is recommended.
7.2.16 Data Write Enable /Disable Command
(DM = “L/H” or LDM, UDM = “L/H”)
During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every
word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to
DQ15.
7.3 Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read
command is issued after tRCD from the Bank Activate command, the data is read out sequentially,
synchronized with both edges of DQS (Burst Read operation). The initial read data becomes
available after CAS Latency from the issuing of the Read command. The CAS Latency must be set
in the Mode Register at power-up.
When the Precharge Operation is performed on a bank during a Burst Read and operation, the
Burst operation is terminated.
When the Read with Auto-precharge command is issued, the Precharge operation is performed
automatically after the Read cycle then the bank is switched to the idle state. This command
cannot be interrupted by any other commands. Refer to the diagrams for Read operation.
- 12 -
Publication Release Date: Oct. 20, 2011
Revision A02
Datasheet pdf - http://www.DataSheet4U.net/

12 Page





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