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PDF W9425G6JH Data sheet ( Hoja de datos )
| Número de pieza | W9425G6JH | |
| Descripción | 4M X 4 BANKS X 16 BITS DDR SDRAM | |
| Fabricantes | Winbond | |
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W9425G6JH
4 M × 4 BANKS × 16 BITS DDR SDRAM
Table of Contents-
1. GENERAL DESCRIPTION.............................................................................................................................4
2. FEATURES ....................................................................................................................................................4
3. KEY PARAMETERS ......................................................................................................................................5
4. PIN CONFIGURATION ..................................................................................................................................6
5. PIN DESCRIPTION........................................................................................................................................7
6. BLOCK DIAGRAM .........................................................................................................................................8
7. FUNCTIONAL DESCRIPTION.......................................................................................................................9
7.1 Power Up Sequence ..........................................................................................................................9
7.2 Command Function ..........................................................................................................................10
7.2.1 Bank Activate Command ......................................................................................................10
7.2.2 Bank Precharge Command ..................................................................................................10
7.2.3 Precharge All Command ......................................................................................................10
7.2.4 Write Command ...................................................................................................................10
7.2.5 Write with Auto-precharge Command...................................................................................10
7.2.6 Read Command ...................................................................................................................10
7.2.7 Read with Auto-precharge Command ..................................................................................10
7.2.8 Mode Register Set Command ..............................................................................................11
7.2.9 Extended Mode Register Set Command ..............................................................................11
7.2.10 No-Operation Command ......................................................................................................11
7.2.11 Burst Read Stop Command..................................................................................................11
7.2.12 Device Deselect Command ..................................................................................................11
7.2.13 Auto Refresh Command .......................................................................................................11
7.2.14 Self Refresh Entry Command...............................................................................................12
7.2.15 Self Refresh Exit Command .................................................................................................12
7.2.16 Data Write Enable /Disable Command .................................................................................12
7.3 Read Operation ................................................................................................................................12
7.4 Write Operation ................................................................................................................................13
7.5 Precharge.........................................................................................................................................13
7.6 Burst Termination .............................................................................................................................13
7.7 Refresh Operation ............................................................................................................................13
7.8 Power Down Mode ...........................................................................................................................14
7.9 Input Clock Frequency Change during Precharge Power Down Mode ............................................14
7.10 Mode Register Operation .................................................................................................................14
7.10.1 Burst Length field (A2 to A0) ................................................................................................14
7.10.2 Addressing Mode Select (A3)...............................................................................................15
Publication Release Date: May 26, 2010
- 1 - Revision A01
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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W9425G6JH
3. KEY PARAMETERS
SYMBOL
DESCRIPTION
CL = 2
tCK Clock Cycle Time
CL = 2.5
CL = 3
tRAS
tRC
IDD0
IDD1
IDD4R
IDD4W
IDD5
IDD6
CL = 4
Active to Precharge Command Period
Active to Ref/Active Command Period
Operating Current: One Bank Active-Precharge
Operating Current: One Bank Active-Read-Precharge
Burst Operation Current
Burst Operation Current
Auto Refresh Burst current
Self-Refresh Current
MIN/MAX.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
-4
-
-
-
-
4 nS
12 nS
4 nS
12 nS
36 nS
52 nS
75 mA
90 mA
140 mA
135 mA
70 mA
2 mA
-5/-5I
7.5 nS
12 nS
6 nS
12 nS
5 nS
12 nS
-
-
40 nS
55 nS
65 mA
80 mA
120 mA
115 mA
65 mA
2 mA
-5-
Publication Release Date: May 26, 2010
Revision A01
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
W9425G6JH
1) READA ≥ tRAS (min) - (BL/2) x tCK
Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command.
2) tRCD(min) ≤ READA < tRAS(min) - (BL/2) x tCK
Data can be read with shortest latency, but the internal Precharge operation does not begin until
after tRAS (min) has completed.
This command must not be interrupted by any other command.
7.2.8 Mode Register Set Command
( RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "L", A0 to A12 = Register Data)
The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst
Length and DLL reset in the Mode Register. The default values in the Mode Register after power-
up are undefined, therefore this command must be issued during the power-up sequence. Also,
this command can be issued while all banks are in the idle state. Refer to the table for specific
codes.
7.2.9 Extended Mode Register Set Command
( RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data)
The Extended Mode Register Set command can be implemented as needed for function
extensions to the standard (SDR-SDRAM). These additional functions include DLL enable/disable,
output drive strength selection. The default value of the extended mode register is not defined;
therefore this command must be issued during the power-up sequence for enabling DLL. Refer to
the table for specific codes.
7.2.10 No-Operation Command
( RAS = "H", CAS = "H", WE = "H")
The No-Operation command simply performs no operation (same command as Device Deselect).
7.2.11 Burst Read Stop Command
( RAS = "H", CAS = "H", WE = "L")
The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.
7.2.12 Device Deselect Command
( CS = "H")
The Device Deselect command disables the command decoder so that the RAS , CAS ,
WE and Address inputs are ignored. This command is similar to the No-Operation command.
7.2.13 Auto Refresh Command
( RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A12 = Don’t Care)
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS–
BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO
- 11 -
Publication Release Date: May 26, 2010
Revision A01
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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