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W947D6HB Schematic ( PDF Datasheet ) - Winbond

Teilenummer W947D6HB
Beschreibung (W947D2HB / W947D6HB) 128Mb Mobile LPDDR
Hersteller Winbond
Logo Winbond Logo 




Gesamt 60 Seiten
W947D6HB Datasheet, Funktion
www.DataSheet.co.kr
W947D6HB / W947D2HB
128Mb Mobile LPDDR
TABLE OF CONTENTS
1. GENERAL DESCRIPTION.......................................................................................................... 4
2. FEATURES.................................................................................................................................. 4
3. PIN CONFIGURATION................................................................................................................ 5
3.1 Ball Assignment: LPDDR X16 ..........................................................................................................5
3.2 Ball Assignment: LPDDR X32 ..........................................................................................................5
4. PIN DESCRIPTION ..................................................................................................................... 6
4.1 Signal Descriptions...........................................................................................................................6
4.2 Addressing Table .............................................................................................................................7
5. BLOCK DIAGRAM ...................................................................................................................... 8
5.1 Block Diagram ..................................................................................................................................8
5.2 Simplified State Diagram ..................................................................................................................9
6. FUNCTION DESCRIPTION....................................................................................................... 10
6.1 Initialization ....................................................................................................................................10
6.1.1 Initialization Flow Diagram ....................................................................................................................11
6.1.2 Initialization Waveform Sequence.........................................................................................................12
6.2 Register Definition ..........................................................................................................................12
6.2.1 Mode Register Set Operation................................................................................................................12
6.2.2 Mode Register Definition .......................................................................................................................13
6.2.3. Burst Length .........................................................................................................................................13
6.3 Burst Definition ...............................................................................................................................14
6.4 Burst Type......................................................................................................................................15
6.5 Read Latency .................................................................................................................................15
6.6 Extended Mode Register Description .............................................................................................15
6.6.1 Extended Mode Register Definition ......................................................................................................16
6.7 Status Register Read .....................................................................................................................16
6.7.1 SRR Register (A[n:0] = 0) .....................................................................................................................17
6.7.2 Status Register Read Timing Diagram .................................................................................................18
6.8 Partial Array Self Refresh ...............................................................................................................19
6.9 Automatic Temperature Compensated Self Refresh.......................................................................19
6.10 Output Drive Strength...................................................................................................................19
6.11 Commands...................................................................................................................................19
6.11.1 Basic Timing Parameters for Commands ...........................................................................................19
6.11.2 Truth Table - Commands ....................................................................................................................20
6.11.3 Truth Table - DM Operations ..............................................................................................................21
6.11.4 Truth Table - CKE ...............................................................................................................................21
6.11.5 Truth Table - Current State BANKn - Command to BANKn ...............................................................22
6.11.6 Truth Table - Current State BANKn, Command to BANKn.................................................................23
7. OPERATION.............................................................................................................................. 24
7.1. Deselect ........................................................................................................................................24
7.2. No Operation .................................................................................................................................24
7.2.1 NOP Command .....................................................................................................................................25
-1-
Publication Release Date:Jun,17, 2011
Revision A01-003
Datasheet pdf - http://www.DataSheet4U.net/






W947D6HB Datasheet, Funktion
www.DataSheet.co.kr
W947D6HB / W947D2HB
128Mb Mobile LPDDR
4. PIN DESCRIPTION
4.1 Signal Descriptions
SIGNAL NAME TYPE FUNCTION
DESCRIPTION
A [n : 0]
Input
Address
Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the opcode
during a MODE REGISTER SET command.
A10 is used for Auto Pre-charge Select.
BA0, BA1
Input
Bank Select
Define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
DQ0~DQ15 (×16)
I/O
DQ0~DQ31 (×32)
Data Input/
Output
Data bus: Input / Output.
CS enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS is
CS Input Chip Select registered HIGH. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the
command code.
RAS
Input
Row Address RAS , CAS and WE (along with CS ) define the command
Strobe
being entered.
CAS
Input
Column Address Referred to RAS
Strobe
WE Input Write Enable Referred to RAS
UDM / LDM(x16); Input
DM0 to DM3 (x32)
CK / CK
Input
Input Mask
Clock Inputs
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading matches
the DQ and DQS loading.
x16: LDM: DQ0 - DQ7, UDM: DQ8 DQ15
x32: DM0: DQ0 - DQ7, DM1: DQ8 DQ15,
DM2: DQ16 DQ23, DM3: DQ24 DQ31
CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of
CK and negative edge of CK .Input and output data is
referenced to the crossing of CK and CK (both directions of
crossing). Internal clock signals are derived from CK/ CK .
-6-
Publication Release Date:Jun,17, 2011
Revision A01-003
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









W947D6HB pdf, datenblatt
www.DataSheet.co.kr
W947D6HB / W947D2HB
6.1.2 Initialization Waveform Sequence
VDD
128Mb Mobile LPDDR
VDDQ
CK
CK
200us
tCK
tRP
tRFC
tRFC
tMRD
tMRD
CKE
Command
NOP
PRE
ARF
ARF
MRS
MRS
ACT
Address
A10
BA0,BA1
DM
DQ,DQS
(High-Z)
All
Banks
CODE
CODE
CODE
CODE
BA0=L
BA1=L
BA0=L
BA1=H
RA
RA
BA
VDD/VDDQ powered up
Clock stable
Load
Mode Reg.
Load
Ext.Mode Reg..
= Don't Care
6.2 Register Definition
6.2.1 Mode Register Set Operation
The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This definition includes
the definition of a burst length, a burst type, a CAS latency as shown in the following figure.
The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will
retain the stored information until it is reprogrammed, the device goes into Deep Power Down mode, or the device
loses power.
Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or interleave), A4-A6 the CAS
latency. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility.
The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must
wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
- 12 -
Publication Release Date:Jun,17, 2011
Revision A01-003
Datasheet pdf - http://www.DataSheet4U.net/

12 Page





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