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PDF EM68932DVKB Data sheet ( Hoja de datos )
| Número de pieza | EM68932DVKB | |
| Descripción | 4M x 32 Mobile DDR Synchronous DRAM | |
| Fabricantes | Etron Technology | |
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EtronTech
EM68932DVKB
4M x 32 Mobile DDR Synchronous DRAM (SDRAM)
Etron Confidential
Advanced (Rev. 1.0 Aug. /2009)
Features
• Fast clock rate: 166/133 MHz
• Differential Clock CK & CK
• Bi-directional DQS
• Four internal banks, 1M x 32-bit for each bank
• Edge-aligned with read data, centered in write data
• Programmable Mode and Extended Mode Registers
- CAS Latency: 2, or 3
- Burst length: 2, 4, or 8
- Burst Type: Sequential & Interleaved
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self
Refresh)
- DS (Drive Strength)
• Individual byte writes mask control
• DM Write Latency = 0
• Precharge Standby Current = 100 µA
• Self Refresh Current = 200 µA
• Deep power-down Current = 10 µA max. at 85℃
• Auto Refresh and Self Refresh
• 4096 refresh cycles / 64ms
• No DLL (Delay Lock Loop), to reduce power; CK to
DQS is not synchronized.
• Power supplies: VDD & VDDQ = +1.8V+0.15V/-0.1V
• Interface: LVCMOS
• Ambient Temperature TA = -25 ~ 85℃,
• 90-ball 8mm x 13mm VFBGA package
- Pb and Halogen Free
Overview
The EM68932D is 134,217,728 bits of double data
rate synchronous DRAM organized as 4 banks of
1,048,576 words by 32 bits. The synchronous
operation with Data Strobe allows extremely high
performance. EM68932D is applied to reduce
leakage and refresh currents while achieving very
high speed. I/O transactions are possible on both
edges of the clock. The ranges of operating
frequencies, programmable burst length and
programmable latencies allow the device to be
useful for a variety of high performance memory
system applications.
Table 1. Ordering Information
Part Number Clock Frequency IDD6 Package
EM68932DVKB-6H
166MHz
EM68932DVKB-75H
133MHz
VK: indicates VFBGA package
200 µA VFBGA
200 µA VFBGA
B: indicates Generation Code
H: indicates Pb and Halogen Free for VFBGA Package
Figure 1. Ball Assignment (Top View)
123 … 789
A VSS DQ31 VSSQ
VDDQ DQ16 VDD
B VDDQ. DQ29 DQ30
C VSSQ DQ27 DQ28
DQ17. DQ18 VSSQ
DQ19 DQ20 VDDQ
D VDDQ DQ25 DQ26
DQ21 DQ22 VSSQ
E VSSQ DQS3 DQ24
DQ23 DQS2 VDDQ
F VDD DM3 NC
NC DM2 VSS
G CKE CK
CK
WE CAS RAS
H A9 A11 NC
CS BA0 BA1
J A6 A7 A8
A10/AP A0
A1
K A4 DM1 A5
A2 DM0 A3
L VSSQ DQS1 DQ8
DQ7 DQS0 VDDQ
M VDDQ DQ9 DQ10
DQ5 DQ6 VSSQ
N VSSQ DQ11 DQ12
DQ3 DQ4 VDDQ
P VDDQ DQ13 DQ14
DQ1 DQ2 VSSQ
R VSS DQ15 VSSQ
VDDQ DQ0 VDD
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
EtronTech
EM68932DVKB
Operation Mode
Table 3 shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command
State CKEn-1 CKEn DM BA1 BA0 A10 A11, A9-0 CS RAS CAS WE
BankActivate
Idle(3)
H X X V V Row Address L L H H
BankPrecharge
Any H X X V V L X L L H L
PrechargeAll
Any H X X X X H X L L H L
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Active(3) H X V V V L
LH L L
Active(3)
H
X VV V
H
Column
Address
L
H
LL
Active(3) H X X V V L A0~A7 L H L H
Active(3) H X X V V H
LH LH
Mode Register Set
Extended Mode Register Set
Idle
Idle
H X XL L
H X XH L
OP code
LL
LL
LL
LL
No-Operation
Any H X X X X X X L H H H
Device Deselect
Any H X X X X X X H X X X
Burst Stop
Active(4) H X X X X X X L H H L
AutoRefresh
Idle H H X X X X X L L L H
SelfRefresh Entry
Idle H L X X X X X L L L H
SelfRefresh Exit
Idle
(Self Refresh)
L
H XX X X
X HX XX
LH HH
Power Down Mode Entry
Idle/Active(5
)
H
L XX X X
HX XX
X
LH HH
Power Down Mode Exit
Any
(Power Down)
L
H XX X X
X HX XX
LH HH
Deep Power Down Entry
Any H L X X X X X L H H L
Deep Power Down Exit
Any L H X X X X X H X X X
Data Mask Enable
Active
H X LX X X
X XX XX
Data Mask Disable
Active
H X HX X X
X XX XX
Note: 1. V = Valid data, X = Don't Care, L = Low level, H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA0, BA1signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
Etron Confidential
5
Rev. 1.0
Aug. 2009
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
EtronTech
EM68932DVKB
z Burst Interruption
Read Interrupted by Read
Burst Read can be interrupted before completion of the burst by a new Read command to any bank. When
the previous burst is interrupted, data bits from the remaining addresses are overridden by data from the
new addresses with the full burst length. The data from the previous Read command continues to appear
on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data
from the interrupting Read command appears. The Read to Read interval is a minimum of 1 clock.
Read Interrupted by Burst Stop & Write
To interrupt Burst Read with a write command, the Burst Stop command must be asserted to avoid data
contention on the I/O bus by placing the DQ (output drivers) in a high impedance state. To ensure the DQ
are tri-stated one cycle before the beginning of the write operation, the Burst Stop command must be
applied at least 2 clock cycles for CL = 2 and at least 3 clock cycles for CL = 3 before the Write command.
Read Interrupted by Precharge
Burst Read can be interrupted by a Precharge of the same bank. A minimum of 1 clock cycle is required for
the read precharge interval. A Precharge command to output disable latency is equivalent to the CAS
latency.
Write Interrupted by Write
A Burst Write can be interrupted by the new Write command before completion of the previous Burst Write,
with the only restriction being that the interval that separates the commands must be at least one clock
cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new
addresses and the new data will be written into the device until the programmed Burst Length is satisfied.
Write Interrupted by Read & DM
A Burst Write can be interrupted by a Read command to any bank. The DQ must be in the high impedance
state at least one clock cycle before the interrupting read data appears on the outputs to avoid data
contention. When the Read command is to be asserted, any residual data from the Burst Write sequence
must be masked by DM. The delay from the last data to the Read command (tWTR) is required to avoid data
contention inside the DRAM. Data presented on the DQ pins before the Read command is initiated will
actually be written to the memory. A Read command interrupting a write sequence can not be issued at the
next clock edge following the Write command.
Write Interrupted by Precharge & DM
A Burst Write can be interrupted by a Precharge of the same bank before completion of the previous burst.
A write recovery time (tWR) is required from the last data to the Precharge command. When the Precharge
command is asserted, any residual data from the Burst Write cycle must be masked by DM.
z Burst Stop Command
The Burst Stop command is initiated by having RAS and CAS High with CS and WE Low at the rising
edge of the clock only. The Burst Stop command has the fewest restrictions, making it the easiest method
to use when terminating a burst operation before it has been completed. When the Burst Stop command is
issued during a Burst Read cycle, both the data and DQS (Data Strobe) go to a high impedance state after
a delay which is equal to the CAS latency set in the Mode Register. The Burst Stop command, however, is
not supported during a Burst Write operation.
Etron Confidential
11
Rev. 1.0
Aug. 2009
Datasheet pdf - http://www.DataSheet4U.net/
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