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PDF AD5760 Data sheet ( Hoja de datos )
| Número de pieza | AD5760 | |
| Descripción | Voltage Output DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5760 (archivo pdf) en la parte inferior de esta página. Total 32 Páginas | ||
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Data Sheet
True 16-Bit, Voltage Output DAC,
±0.5 LSB INL, ±0.5 LSB DNL
AD5760
FEATURES
True 16-bit voltage output DAC, ±0.5 LSB INL
8 nV/√Hz output noise spectral density
0.00625 LSB long-term linearity error stability
±0.018 ppm/°C gain error temperature coefficient
2.5 μs output voltage settling time
3.5 nV-sec midscale glitch impulse
Integrated precision reference buffers
Operating temperature range: −40°C to +125°C
4 mm × 5 mm LFCSP package
Wide power supply range of up to ±16.5 V
35 MHz Schmitt triggered digital interface
1.8 V-compatible digital interface
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
GENERAL DESCRIPTION
The AD57601 is a true 16-bit, unbuffered voltage output DAC
that operates from a bipolar supply of up to 33 V. The AD5760
accepts a positive reference input range of 5 V to VDD − 2.5 V
and a negative reference input range of VSS + 2.5 V to 0 V. The
AD5760 offers a relative accuracy specification of ±0.5 LSB
maximum range, and operation is guaranteed monotonic with a
±0.5 LSB DNL maximum range specification.
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 35 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, and DSP interface standards. The
part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V in a known output impedance
state and remains in this state until a valid write to the device
takes place. The part provides an output clamp feature that
places the output in a defined load state.
FUNCTIONAL BLOCK DIAGRAM
VCC
VDD
VREFP
IOVCC
SDIN
SCLK
SYNC
SDO
LDAC
CLR
RESET
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
16
DAC 16
REG
16-BIT
DAC
POWER-ON RESET
AND CLEAR LOGIC
DGND
VSS AGND
VREFN
Figure 1.
6.8kΩ 6.8kΩ
A1
R1 RFB
RFB
INV
VOUT
6kΩ
AD5760
Table 1. Related Devices
Part No.
AD5790
AD5791
AD5780
AD5781
AD5541A/AD5542A
Description
20-bit, 2 LSB accurate DAC
20-bit, 1 LSB accurate DAC
18-bit, 1 LSB accurate DAC
18-bit, 0.5 LSB INL
16-bit, 1 LSB accurate 5 V DAC
PRODUCT HIGHLIGHTS
1. True 16-bit accuracy.
2. Wide power supply range of up to ±16.5 V.
3. −40°C to +125°C operating temperature range.
4. Low 8 nV/√Hz noise.
5. Low ±0.018 ppm/°C gain error temperature coefficient.
COMPANION PRODUCTS
Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1
External Reference: ADR445
DC-to-DC Design Tool: ADIsimPower™
Additional companion products on the AD5780 product page
1 Protected by U.S. Patent No. 7,884,747. Other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
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1 page  
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Data Sheet
AD5760
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
Limit1
IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V
40 28
92 60
15 10
95
55
22
48 40
86
97
12 7
13 10
20 16
14 11
130 130
130 130
50 50
140 140
00
65 60
62 45
00
35 35
150 150
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns min
ns typ
ns min
ns max
ns max
ns min
ns typ
ns typ
Test Conditions/Comments
SCLK cycle time
SCLK cycle time (readback and daisy-chain modes)
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge hold time
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignore
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
LDAC falling edge to output response time
SYNC rising edge to output response time (LDAC tied low)
CLR pulse width low
CLR pulse activation time
SYNC falling edge to first SCLK rising edge
SYNC rising edge to SDO tristate (CL = 50 pF)
SCLK rising edge to SDO valid (CL = 50 pF)
SYNC rising edge to SCLK rising edge ignore
RESET pulse width low
RESET pulse activation time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes.
Rev. 0 | Page 5 of 32
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Data Sheet
AD5760
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0.08
0.06
VVVVRRDSSEEDFF==PN–+==115+–5V11V00VV
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
0
10000
20000
30000
AD8675 OUTPUT BUFFER
TA = 25°C
40000 50000 60000 70000
DAC CODE
Figure 6. Integral Nonlinearity Error vs. DAC Code, ±10 V Span
0.15
0.10
VVVVRRDSSDEEFF==PN–+==115+05V1VV0V
0.05
0
–0.05
–0.10
0
10000
20000
30000
AD8675 OUTPUT BUFFER
TA = 25°C
40000 50000 60000 70000
DAC CODE
Figure 7. Integral Nonlinearity Error vs. DAC Code, 10 V Span
0.10
0.05
VVVVRRDSSEEDFF==PN
= +5V
= 0V
+15V
–15V
0
–0.05
–0.10
–0.15
–0.20
0
10000
20000
30000
AD8675 OUTPUT BUFFER
TA = 25°C
40000 50000 60000 70000
DAC CODE
Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span
0.10
0.05
VVVVRRDSSEEDFF==PN–+==115+05VV5VV
0
–0.05
–0.10
–0.15
–0.20
0
10000
20000
30000
AD8675 OUTPUT BUFFER
TA = 25°C
40000 50000 60000 70000
DAC CODE
Figure 9. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode
0.10
0.08
0.06
VVVVRRDSSEEDFF==PN–+==115+–5V11V00VV
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
0
10000
20000
30000
AD8675 OUTPUT BUFFER
TA = 25°C
40000 50000 60000 70000
DAC CODE
Figure 10. Differential Nonlinearity Error vs. DAC Code, ±10 V Span
0.20
0.15
VVVVRRDSSEEDFF==PN
= +10V
= 0V
+15V
–15V
0.10
0.05
0
–0.05
–0.10
0
10000
20000
30000
AD8675 OUTPUT BUFFER
TA = 25°C
40000 50000 60000 70000
DAC CODE
Figure 11. Differential Nonlinearity Error vs. DAC Code, 10 V Span
Rev. 0 | Page 11 of 32
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| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet AD5760.PDF ] | |
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