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Teilenummer | P40NF10 |
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Beschreibung | STP40NF10 | |
Hersteller | STMicroelectronics | |
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Gesamt 11 Seiten www.DataSheet.co.kr
STP40NF10
STB40NF10 - STB40NF10-1
N-CHANNEL 100V - 0.024Ω - 50A TO-220/D2PAK/I2PAK
LOW GATE CHARGE STripFET™ II POWER MOSFET
TYPE
VDSS
RDS(on)
ID
STP40NF10
www.DataSheet4U.cSoTmB40NF10
STB40NF10-1
100 V
100 V
100 V
< 0.028 Ω
< 0.028 Ω
< 0.028 Ω
50 A
50 A
50 A
s TYPICAL RDS(on) = 0.024Ω
s EXCEPTIONAL dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s APPLICATION ORIENTED
CHARACTERIZATION
s ADD SUFFIX “T4” FOR ORDERING IN TAPE &
REEL
3
2
1
TO-220
3
1
D2PAK
123
I2PAK
DESCRIPTION
This Power MOSFET series realized with STMicro-
electronics unique STripFET process has specifical-
ly been designed to minimize input capacitance and
gate charge. It is therefore suitable as primary
switch in advanced high-efficiency isolated DC-DC
converters for Telecom and Computer application. It
is also intended for any application with low gate
charge drive requirements.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s HIGH-EFFICIENCY DC-DC CONVERTERS
s UPS AND MOTOR CONTROL
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS
VDGR
VGS
ID(*)
ID
IDM (l)
PTOT
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
Drain Current (pulsed)
Total Dissipation at TC = 25°C
Derating Factor
dv/dt (1) Peak Diode Recovery voltage slope
EAS (2)
Tstg
Single Pulse Avalanche Energy
Storage Temperature
Tj Operating Junction Temperature
(q) Pulse width limited by safe operating area
(*) Limited by Package
September 2002
Value
100
100
± 20
50
35
200
150
1
20
150
Unit
V
V
V
A
A
A
W
W/°C
V/ns
mJ
– 55 to 175
°C
(1) ISD ≤40A, di/dt ≤600A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.
(2) Starting Tj = 25°C, ID = 40A, VDD = 50V
1/11
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
STP40NF10 - STB40NF10 - STB40NF10-1
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
www.DataSheet4U.com
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/11
Datasheet pdf - http://www.DataSheet4U.net/
6 Page | ||
Seiten | Gesamt 11 Seiten | |
PDF Download | [ P40NF10 Schematic.PDF ] |
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